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Merge remote-tracking branch 'origin/xaig' into xc7mux

This commit is contained in:
Eddie Hung 2019-06-24 22:48:49 -07:00
parent f1675b88f6 a19226c174
commit 1564eb8b54
8 changed files with 104 additions and 10 deletions
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4
backends/json/json.cc
View File

@ -126,6 +126,10 @@ struct JsonWriter
f << stringf("%s\n", first ? "" : ",");
f << stringf(" %s: {\n", get_name(n).c_str());
f << stringf(" \"direction\": \"%s\",\n", w->port_input ? w->port_output ? "inout" : "input" : "output");
if (w->start_offset)
f << stringf(" \"offset\": %d,\n", w->start_offset);
if (w->upto)
f << stringf(" \"upto\": 1,\n");
f << stringf(" \"bits\": %s\n", get_bits(w).c_str());
f << stringf(" }");
first = false;

12
frontends/json/jsonparse.cc
View File

@ -292,6 +292,18 @@ void json_import(Design *design, string &modname, JsonNode *node)
if (port_wire == nullptr)
port_wire = module->addWire(port_name, GetSize(port_bits_node->data_array));
if (port_node->data_dict.count("upto") != 0) {
JsonNode *val = port_node->data_dict.at("upto");
if (val->type == 'N')
port_wire->upto = val->data_number != 0;
}
if (port_node->data_dict.count("offset") != 0) {
JsonNode *val = port_node->data_dict.at("offset");
if (val->type == 'N')
port_wire->start_offset = val->data_number;
}
if (port_direction_node->data_string == "input") {
port_wire->port_input = true;
} else

61
passes/techmap/abc9.cc
View File

@ -80,9 +80,6 @@ void handle_loops(RTLIL::Design *design)
{
Pass::call(design, "scc -set_attr abc_scc_id {}");
design->selection_stack.emplace_back(false);
RTLIL::Selection& sel = design->selection_stack.back();
// For every unique SCC found, (arbitrarily) find the first
// cell in the component, and select (and mark) all its output
// wires
@ -92,24 +89,70 @@ void handle_loops(RTLIL::Design *design)
if (it != cell->attributes.end()) {
auto r = ids_seen.insert(it->second);
if (r.second) {
for (const auto &c : cell->connections()) {
for (auto &c : cell->connections_) {
if (c.second.is_fully_const()) continue;
if (cell->output(c.first)) {
SigBit b = c.second.as_bit();
Wire *w = b.wire;
log_assert(!w->port_input);
w->port_input = true;
w = module->wire(stringf("%s.abci", w->name.c_str()));
if (!w) {
w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
w->port_output = true;
}
else {
log_assert(w->port_input);
log_assert(b.offset < GetSize(w));
}
w->set_bool_attribute("\\abc_scc_break");
sel.select(module, w);
module->swap_names(b.wire, w);
c.second = RTLIL::SigBit(w, b.offset);
}
}
}
cell->attributes.erase(it);
}
RTLIL::Module* box_module = design->module(cell->type);
if (box_module) {
auto jt = box_module->attributes.find("\\abc_scc_break");
if (jt != box_module->attributes.end()) {
auto it = cell->connections_.find(RTLIL::escape_id(jt->second.decode_string()));
if (it == cell->connections_.end())
log_error("abc_scc_break attribute value '%s' does not exist as port on module '%s'\n", jt->second.decode_string().c_str(), log_id(box_module));
log_assert(it != cell->connections_.end());
RTLIL::SigSpec sig;
for (auto b : it->second) {
Wire *w = b.wire;
if (w->port_output) {
log_assert(w->get_bool_attribute("\\abc_scc_break"));
w = module->wire(stringf("%s.abci", w->name.c_str()));
log_assert(w);
log_assert(b.offset < GetSize(w));
log_assert(w->port_input);
}
else {
log_assert(!w->port_output);
w->port_output = true;
w->set_bool_attribute("\\abc_scc_break");
w = module->wire(stringf("%s.abci", w->name.c_str()));
if (!w) {
w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
w->port_input = true;
}
else {
log_assert(w->port_input);
log_assert(b.offset < GetSize(w));
}
}
sig.append(RTLIL::SigBit(w, b.offset));
}
it->second = sig;
}
}
}
// Then cut those selected wires to expose them as new PO/PI
Pass::call(design, "expose -cut -sep .abc");
design->selection_stack.pop_back();
module->fixup_ports();
}
std::string add_echos_to_abc_cmd(std::string str)

2
techlibs/ecp5/cells_sim.v
View File

@ -106,7 +106,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
endmodule
// ---------------------------------------
//(* abc_box_id=2 *)
(* abc_box_id=2, abc_scc_break="DI" *)
module TRELLIS_DPR16X4 (
input [3:0] DI,
input [3:0] WAD,

14
techlibs/xilinx/abc_xc7.box
View File

@ -34,3 +34,17 @@ CARRY4 3 1 10 8
494 465 445 - - 433 469 - - 157
592 540 520 356 - 512 548 292 - 228
580 526 507 398 385 508 528 378 380 114
# SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
# Outputs: DPO SPO
RAM64X1D 4 0 15 2
- - - - - - - 124 124 124 124 124 124 - -
124 124 124 124 124 124 - - - - - - 124 - -
# SLICEM/A6LUT + F7[AB]MUX
# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
# Outputs: DPO SPO
RAM128X1D 5 0 17 2
- - - - - - - - 314 314 314 314 314 314 292 - -
347 347 347 347 347 347 296 - - - - - - - - - -

2
techlibs/xilinx/cells_sim.v
View File

@ -306,6 +306,7 @@ module RAM32X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
(* abc_box_id = 4, abc_scc_break="D" *)
module RAM64X1D (
output DPO, SPO,
input D, WCLK, WE,
@ -323,6 +324,7 @@ module RAM64X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
(* abc_box_id = 5, abc_scc_break="D" *)
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,

5
tests/various/abc9.v Normal file
View File

@ -0,0 +1,5 @@
module abc9_test027(output reg o);
initial o = 1'b0;
always @*
o <= ~o;
endmodule

14
tests/various/abc9.ys Normal file
View File

@ -0,0 +1,14 @@
read_verilog abc9.v
proc
design -save gold
abc9 -lut 4
check
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter