riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Back to passing all xc7srl tests!

This commit is contained in:
Eddie Hung 2019-05-01 18:23:21 -07:00
parent 31ff0d8ef5
commit d394b9301b
1 changed files with 4 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
techlibs/xilinx/synth_xilinx.cc
View File

@ -205,17 +205,16 @@ struct SynthXilinxPass : public ScriptPass
}
if (check_label("fine")) {
run("opt -fast");
run("memory_map");
run("dffsr2dff");
run("dff2dffe");
// shregmap -tech xilinx can cope with $shiftx and $mux
// cells for identifiying variable-length shift registers,
// so attempt to convert $pmux-es to the former
if (!nosrl || help_mode)
run("pmux2shiftx", "(skip if '-nosrl')");
run("opt -fast -full");
run("memory_map");
run("dffsr2dff");
run("dff2dffe");
run("opt -full");
if (!vpr || help_mode)