mirror of https://github.com/YosysHQ/yosys.git
mux_map to no longer copy last value into 1'bx
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8bce3fb329
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@ -35,23 +35,6 @@ module \$shiftx (A, B, Y);
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
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generate
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genvar i;
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wire [A_WIDTH-1:0] A_forward;
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assign A_backward[A_WIDTH-1] = A[A_WIDTH-1];
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for (i = A_WIDTH-2; i >= 0; i = i - 1)
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if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'bx)
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assign A_backward[i] = A_backward[i+1];
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else
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assign A_backward[i] = A[i];
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wire [A_WIDTH-1:0] A_without_x;
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assign A_without_x[0] = A_backward[0];
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for (i = 1; i < A_WIDTH; i = i + 1)
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if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'bx)
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assign A_without_x[i] = A_without_x[i-1];
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else
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assign A_without_x[i] = A[i];
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if (B_SIGNED) begin
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if (B_WIDTH < 4 || A_WIDTH <= 4)
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wire _TECHMAP_FAIL_ = 1;
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@ -64,7 +47,7 @@ module \$shiftx (A, B, Y);
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.B_WIDTH(B_WIDTH-1'd1),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A_without_x), .B(B[B_WIDTH-2:0]), .Y(Y)
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.A(A), .B(B[B_WIDTH-2:0]), .Y(Y)
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);
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else
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wire _TECHMAP_FAIL_ = 1;
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@ -80,7 +63,7 @@ module \$shiftx (A, B, Y);
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A_without_x), .B(B), .Y(Y)
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.A(A), .B(B), .Y(Y)
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);
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end
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endgenerate
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