mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #381 from azonenberg/countfix
Added better behavioral models for GreenPAK counters. Refactored cells_sim into two files so analog/mixed signal stuff is separate
This commit is contained in:
Clifford Wolf
GitHub
commit
2cf0b5c157
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@ -6,4 +6,6 @@ OBJS += techlibs/greenpak4/greenpak4_dffinv.o
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$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_latch.v))
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$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_map.v))
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$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim.v))
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$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim_ams.v))
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$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim_digital.v))
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$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/gp_dff.lib))
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@ -1,141 +1,9 @@
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`timescale 1ns/1ps
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module GP_2LUT(input IN0, IN1, output OUT);
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parameter [3:0] INIT = 0;
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assign OUT = INIT[{IN1, IN0}];
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endmodule
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`include "cells_sim_ams.v"
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`include "cells_sim_digital.v"
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module GP_3LUT(input IN0, IN1, IN2, output OUT);
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parameter [7:0] INIT = 0;
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assign OUT = INIT[{IN2, IN1, IN0}];
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endmodule
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module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
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parameter [15:0] INIT = 0;
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assign OUT = INIT[{IN3, IN2, IN1, IN0}];
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endmodule
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module GP_ABUF(input wire IN, output wire OUT);
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assign OUT = IN;
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//must be 1, 5, 20, 50
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//values >1 only available with Vdd > 2.7V
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parameter BANDWIDTH_KHZ = 1;
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//cannot simulate mixed signal IP
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endmodule
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module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
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parameter BANDWIDTH = "HIGH";
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parameter VIN_ATTEN = 1;
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parameter VIN_ISRC_EN = 0;
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parameter HYSTERESIS = 0;
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initial OUT = 0;
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//cannot simulate mixed signal IP
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endmodule
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module GP_BANDGAP(output reg OK);
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parameter AUTO_PWRDN = 1;
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parameter CHOPPER_EN = 1;
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parameter OUT_DELAY = 100;
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//cannot simulate mixed signal IP
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endmodule
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module GP_CLKBUF(input wire IN, output wire OUT);
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assign OUT = IN;
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endmodule
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module GP_COUNT8(input CLK, input wire RST, output reg OUT, output reg[7:0] POUT);
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parameter RESET_MODE = "RISING";
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parameter COUNT_TO = 8'h1;
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parameter CLKIN_DIVIDE = 1;
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//more complex hard IP blocks are not supported for simulation yet
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reg[7:0] count = COUNT_TO;
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//Combinatorially output whenever we wrap low
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always @(*) begin
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OUT <= (count == 8'h0);
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OUT <= count;
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end
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//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
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//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
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//Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
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always @(posedge CLK) begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_TO;
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/*
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if((RESET_MODE == "RISING") && RST)
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count <= 0;
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if((RESET_MODE == "FALLING") && !RST)
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count <= 0;
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if((RESET_MODE == "BOTH") && RST)
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count <= 0;
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*/
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end
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endmodule
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module GP_COUNT14(input CLK, input wire RST, output reg OUT);
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parameter RESET_MODE = "RISING";
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parameter COUNT_TO = 14'h1;
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parameter CLKIN_DIVIDE = 1;
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//more complex hard IP blocks are not supported for simulation yet
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endmodule
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module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
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input UP, input KEEP, output reg[7:0] POUT);
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parameter RESET_MODE = "RISING";
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parameter RESET_VALUE = "ZERO";
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parameter COUNT_TO = 8'h1;
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parameter CLKIN_DIVIDE = 1;
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//more complex hard IP blocks are not supported for simulation yet
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endmodule
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module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
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input UP, input KEEP, output reg[7:0] POUT);
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parameter RESET_MODE = "RISING";
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parameter RESET_VALUE = "ZERO";
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parameter COUNT_TO = 14'h1;
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parameter CLKIN_DIVIDE = 1;
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//more complex hard IP blocks are not supported for simulation yet
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endmodule
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module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
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initial VOUT = 0;
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//analog hard IP is not supported for simulation
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endmodule
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//Cells still in this file have INCOMPLETE simulation models, need to finish them
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module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL);
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parameter PWRDN_SYNC = 1'b0;
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@ -159,237 +27,6 @@ module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output re
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endmodule
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module GP_DCMPREF(output reg[7:0]OUT);
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parameter[7:0] REF_VAL = 8'h00;
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initial OUT = REF_VAL;
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endmodule
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module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
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always @(*) begin
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case(SEL)
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2'd00: begin
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OUTA <= IN0;
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OUTB <= IN3;
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end
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2'd01: begin
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OUTA <= IN1;
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OUTB <= IN2;
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end
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2'd02: begin
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OUTA <= IN2;
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OUTB <= IN1;
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end
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2'd03: begin
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OUTA <= IN3;
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OUTB <= IN0;
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end
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endcase
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end
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endmodule
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module GP_DELAY(input IN, output reg OUT);
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parameter DELAY_STEPS = 1;
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parameter GLITCH_FILTER = 0;
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initial OUT = 0;
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generate
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//TODO: These delays are PTV dependent! For now, hard code 3v3 timing
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//Change simulation-mode delay depending on global Vdd range (how to specify this?)
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always @(*) begin
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case(DELAY_STEPS)
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1: #166 OUT = IN;
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2: #318 OUT = IN;
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2: #471 OUT = IN;
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3: #622 OUT = IN;
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default: begin
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$display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
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$finish;
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end
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endcase
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end
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endgenerate
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endmodule
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module GP_DFF(input D, CLK, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK) begin
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Q <= D;
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end
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endmodule
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module GP_DFFI(input D, CLK, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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initial nQ = INIT;
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always @(posedge CLK) begin
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nQ <= ~D;
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end
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endmodule
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module GP_DFFR(input D, CLK, nRST, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nRST) begin
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if (!nRST)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule
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module GP_DFFRI(input D, CLK, nRST, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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initial nQ = INIT;
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always @(posedge CLK, negedge nRST) begin
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if (!nRST)
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nQ <= 1'b1;
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else
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nQ <= ~D;
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end
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endmodule
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module GP_DFFS(input D, CLK, nSET, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nSET) begin
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if (!nSET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule
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module GP_DFFSI(input D, CLK, nSET, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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initial nQ = INIT;
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always @(posedge CLK, negedge nSET) begin
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if (!nSET)
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nQ <= 1'b0;
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else
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nQ <= ~D;
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end
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endmodule
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module GP_DFFSR(input D, CLK, nSR, output reg Q);
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parameter [0:0] INIT = 1'bx;
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parameter [0:0] SRMODE = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nSR) begin
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if (!nSR)
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Q <= SRMODE;
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else
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Q <= D;
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end
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endmodule
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module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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parameter [0:0] SRMODE = 1'bx;
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initial nQ = INIT;
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always @(posedge CLK, negedge nSR) begin
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if (!nSR)
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nQ <= ~SRMODE;
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else
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nQ <= ~D;
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end
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endmodule
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module GP_DLATCH(input D, input nCLK, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(*) begin
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if(!nCLK)
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Q <= D;
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end
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endmodule
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module GP_DLATCHI(input D, input nCLK, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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initial nQ = INIT;
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always @(*) begin
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if(!nCLK)
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nQ <= ~D;
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end
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endmodule
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module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(*) begin
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if(!nRST)
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Q <= 1'b0;
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else if(!nCLK)
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Q <= D;
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end
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endmodule
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module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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initial nQ = INIT;
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always @(*) begin
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if(!nRST)
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nQ <= 1'b1;
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else if(!nCLK)
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nQ <= ~D;
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end
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endmodule
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module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(*) begin
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if(!nSET)
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Q <= 1'b1;
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else if(!nCLK)
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Q <= D;
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end
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endmodule
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module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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initial nQ = INIT;
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always @(*) begin
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if(!nSET)
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nQ <= 1'b0;
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else if(!nCLK)
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nQ <= ~D;
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end
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endmodule
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module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
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parameter [0:0] INIT = 1'bx;
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parameter[0:0] SRMODE = 1'bx;
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initial Q = INIT;
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always @(*) begin
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if(!nSR)
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Q <= SRMODE;
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else if(!nCLK)
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Q <= D;
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end
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endmodule
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module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
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parameter [0:0] INIT = 1'bx;
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parameter[0:0] SRMODE = 1'bx;
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initial nQ = INIT;
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always @(*) begin
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if(!nSR)
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nQ <= ~SRMODE;
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else if(!nCLK)
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nQ <= ~D;
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end
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endmodule
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module GP_EDGEDET(input IN, output reg OUT);
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parameter EDGE_DIRECTION = "RISING";
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@ -400,107 +37,6 @@ module GP_EDGEDET(input IN, output reg OUT);
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endmodule
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module GP_IBUF(input IN, output OUT);
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assign OUT = IN;
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endmodule
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module GP_IOBUF(input IN, input OE, output OUT, inout IO);
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assign OUT = IO;
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assign IO = OE ? IN : 1'bz;
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endmodule
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module GP_INV(input IN, output OUT);
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assign OUT = ~IN;
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endmodule
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module GP_LFOSC(input PWRDN, output reg CLKOUT);
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parameter PWRDN_EN = 0;
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parameter AUTO_PWRDN = 0;
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parameter OUT_DIV = 1;
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initial CLKOUT = 0;
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//auto powerdown not implemented for simulation
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//output dividers not implemented for simulation
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always begin
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if(PWRDN)
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CLKOUT = 0;
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else begin
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//half period of 1730 Hz
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#289017;
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CLKOUT = ~CLKOUT;
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end
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end
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endmodule
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module GP_OBUF(input IN, output OUT);
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assign OUT = IN;
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endmodule
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module GP_OBUFT(input IN, input OE, output OUT);
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assign OUT = OE ? IN : 1'bz;
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endmodule
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module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
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parameter GAIN = 1;
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parameter INPUT_MODE = "SINGLE";
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initial VOUT = 0;
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//cannot simulate mixed signal IP
|
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endmodule
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module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
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initial OUT = 0;
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parameter PATTERN_DATA = 16'h0;
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parameter PATTERN_LEN = 5'd16;
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reg[3:0] count = 0;
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always @(posedge CLK) begin
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if(!nRST)
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OUT <= PATTERN_DATA[0];
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|
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else begin
|
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count <= count + 1;
|
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OUT <= PATTERN_DATA[count];
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|
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if( (count + 1) == PATTERN_LEN)
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count <= 0;
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end
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end
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endmodule
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module GP_PWRDET(output reg VDD_LOW);
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initial VDD_LOW = 0;
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endmodule
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module GP_POR(output reg RST_DONE);
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parameter POR_TIME = 500;
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|
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initial begin
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RST_DONE = 0;
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|
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if(POR_TIME == 4)
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#4000;
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else if(POR_TIME == 500)
|
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#500000;
|
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else begin
|
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$display("ERROR: bad POR_TIME for GP_POR cell");
|
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$finish;
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end
|
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|
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RST_DONE = 1;
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|
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end
|
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|
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endmodule
|
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module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
|
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|
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parameter PWRDN_EN = 0;
|
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|
|
@ -567,29 +103,6 @@ module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRI
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|||
|
||||
endmodule
|
||||
|
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module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
|
||||
|
||||
parameter OUTA_TAP = 1;
|
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parameter OUTA_INVERT = 0;
|
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parameter OUTB_TAP = 1;
|
||||
|
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reg[15:0] shreg = 0;
|
||||
|
||||
always @(posedge CLK, negedge nRST) begin
|
||||
|
||||
if(!nRST)
|
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shreg = 0;
|
||||
|
||||
else
|
||||
shreg <= {shreg[14:0], IN};
|
||||
|
||||
end
|
||||
|
||||
assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
|
||||
assign OUTB = shreg[OUTB_TAP - 1];
|
||||
|
||||
endmodule
|
||||
|
||||
module GP_SPI(
|
||||
input SCK,
|
||||
inout SDAT,
|
||||
|
|
@ -625,17 +138,3 @@ module GP_SYSRESET(input RST);
|
|||
//cannot simulate whole system reset
|
||||
|
||||
endmodule
|
||||
|
||||
module GP_VDD(output OUT);
|
||||
assign OUT = 1;
|
||||
endmodule
|
||||
|
||||
module GP_VREF(input VIN, output reg VOUT);
|
||||
parameter VIN_DIV = 1;
|
||||
parameter VREF = 0;
|
||||
//cannot simulate mixed signal IP
|
||||
endmodule
|
||||
|
||||
module GP_VSS(output OUT);
|
||||
assign OUT = 0;
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -0,0 +1,110 @@
|
|||
`timescale 1ns/1ps
|
||||
|
||||
/*
|
||||
This file contains analog / mixed signal cells, or other things that are not possible to fully model
|
||||
in behavioral Verilog.
|
||||
|
||||
It also contains some stuff like oscillators that use non-synthesizeable constructs such as delays.
|
||||
TODO: do we want a third file for those cells?
|
||||
*/
|
||||
|
||||
module GP_ABUF(input wire IN, output wire OUT);
|
||||
|
||||
assign OUT = IN;
|
||||
|
||||
//must be 1, 5, 20, 50
|
||||
//values >1 only available with Vdd > 2.7V
|
||||
parameter BANDWIDTH_KHZ = 1;
|
||||
|
||||
endmodule
|
||||
|
||||
module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
|
||||
|
||||
parameter BANDWIDTH = "HIGH";
|
||||
parameter VIN_ATTEN = 1;
|
||||
parameter VIN_ISRC_EN = 0;
|
||||
parameter HYSTERESIS = 0;
|
||||
|
||||
initial OUT = 0;
|
||||
|
||||
endmodule
|
||||
|
||||
module GP_BANDGAP(output reg OK);
|
||||
parameter AUTO_PWRDN = 1;
|
||||
parameter CHOPPER_EN = 1;
|
||||
parameter OUT_DELAY = 100;
|
||||
|
||||
endmodule
|
||||
|
||||
module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
|
||||
|
||||
initial VOUT = 0;
|
||||
|
||||
//analog hard IP is not supported for simulation
|
||||
|
||||
endmodule
|
||||
|
||||
module GP_LFOSC(input PWRDN, output reg CLKOUT);
|
||||
|
||||
parameter PWRDN_EN = 0;
|
||||
parameter AUTO_PWRDN = 0;
|
||||
parameter OUT_DIV = 1;
|
||||
|
||||
initial CLKOUT = 0;
|
||||
|
||||
//auto powerdown not implemented for simulation
|
||||
//output dividers not implemented for simulation
|
||||
|
||||
always begin
|
||||
if(PWRDN)
|
||||
CLKOUT = 0;
|
||||
else begin
|
||||
//half period of 1730 Hz
|
||||
#289017;
|
||||
CLKOUT = ~CLKOUT;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
|
||||
|
||||
parameter GAIN = 1;
|
||||
parameter INPUT_MODE = "SINGLE";
|
||||
|
||||
initial VOUT = 0;
|
||||
|
||||
//cannot simulate mixed signal IP
|
||||
|
||||
endmodule
|
||||
|
||||
module GP_PWRDET(output reg VDD_LOW);
|
||||
initial VDD_LOW = 0;
|
||||
endmodule
|
||||
|
||||
module GP_VREF(input VIN, output reg VOUT);
|
||||
parameter VIN_DIV = 1;
|
||||
parameter VREF = 0;
|
||||
//cannot simulate mixed signal IP
|
||||
endmodule
|
||||
|
||||
module GP_POR(output reg RST_DONE);
|
||||
parameter POR_TIME = 500;
|
||||
|
||||
initial begin
|
||||
RST_DONE = 0;
|
||||
|
||||
if(POR_TIME == 4)
|
||||
#4000;
|
||||
else if(POR_TIME == 500)
|
||||
#500000;
|
||||
else begin
|
||||
$display("ERROR: bad POR_TIME for GP_POR cell");
|
||||
$finish;
|
||||
end
|
||||
|
||||
RST_DONE = 1;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,785 @@
|
|||
`timescale 1ns/1ps
|
||||
|
||||
/*
|
||||
This file contains simulation models for GreenPAK cells which are possible to fully model using synthesizeable
|
||||
behavioral Verilog constructs only.
|
||||
*/
|
||||
|
||||
module GP_2LUT(input IN0, IN1, output OUT);
|
||||
parameter [3:0] INIT = 0;
|
||||
assign OUT = INIT[{IN1, IN0}];
|
||||
endmodule
|
||||
|
||||
module GP_3LUT(input IN0, IN1, IN2, output OUT);
|
||||
parameter [7:0] INIT = 0;
|
||||
assign OUT = INIT[{IN2, IN1, IN0}];
|
||||
endmodule
|
||||
|
||||
module GP_4LUT(
|
||||
input wire IN0,
|
||||
input wire IN1,
|
||||
input wire IN2,
|
||||
input wire IN3,
|
||||
output wire OUT);
|
||||
|
||||
parameter [15:0] INIT = 0;
|
||||
assign OUT = INIT[{IN3, IN2, IN1, IN0}];
|
||||
endmodule
|
||||
|
||||
module GP_CLKBUF(input wire IN, output wire OUT);
|
||||
assign OUT = IN;
|
||||
endmodule
|
||||
|
||||
module GP_COUNT14(input CLK, input wire RST, output reg OUT);
|
||||
|
||||
parameter RESET_MODE = "RISING";
|
||||
|
||||
parameter COUNT_TO = 14'h1;
|
||||
parameter CLKIN_DIVIDE = 1;
|
||||
|
||||
reg[13:0] count = COUNT_TO;
|
||||
|
||||
initial begin
|
||||
if(CLKIN_DIVIDE != 1) begin
|
||||
$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
//Combinatorially output underflow flag whenever we wrap low
|
||||
always @(*) begin
|
||||
OUT <= (count == 14'h0);
|
||||
end
|
||||
|
||||
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
|
||||
//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
|
||||
generate
|
||||
case(RESET_MODE)
|
||||
|
||||
"RISING": begin
|
||||
always @(posedge CLK, posedge RST) begin
|
||||
count <= count - 1'd1;
|
||||
if(count == 0)
|
||||
count <= COUNT_TO;
|
||||
|
||||
if(RST)
|
||||
count <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
"FALLING": begin
|
||||
always @(posedge CLK, negedge RST) begin
|
||||
count <= count - 1'd1;
|
||||
if(count == 0)
|
||||
count <= COUNT_TO;
|
||||
|
||||
if(!RST)
|
||||
count <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
"BOTH": begin
|
||||
initial begin
|
||||
$display("Both-edge reset mode for GP_COUNT14 not implemented");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
"LEVEL": begin
|
||||
always @(posedge CLK, posedge RST) begin
|
||||
if(RST)
|
||||
count <= 0;
|
||||
|
||||
else begin
|
||||
count <= count - 1'd1;
|
||||
if(count == 0)
|
||||
count <= COUNT_TO;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
default: begin
|
||||
initial begin
|
||||
$display("Invalid RESET_MODE on GP_COUNT8");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endcase
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
|
||||
input UP, input KEEP, output reg[7:0] POUT);
|
||||
|
||||
parameter RESET_MODE = "RISING";
|
||||
parameter RESET_VALUE = "ZERO";
|
||||
|
||||
parameter COUNT_TO = 14'h1;
|
||||
parameter CLKIN_DIVIDE = 1;
|
||||
|
||||
initial begin
|
||||
if(CLKIN_DIVIDE != 1) begin
|
||||
$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
reg[13:0] count = COUNT_TO;
|
||||
|
||||
//Combinatorially output underflow flag whenever we wrap low
|
||||
always @(*) begin
|
||||
if(UP)
|
||||
OUT <= (count == 14'h3fff);
|
||||
else
|
||||
OUT <= (count == 14'h0);
|
||||
POUT <= count[7:0];
|
||||
end
|
||||
|
||||
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
|
||||
//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
|
||||
generate
|
||||
case(RESET_MODE)
|
||||
|
||||
"RISING": begin
|
||||
always @(posedge CLK, posedge RST) begin
|
||||
|
||||
//Main counter
|
||||
if(KEEP) begin
|
||||
end
|
||||
else if(UP)
|
||||
count <= count + 1'd1;
|
||||
else
|
||||
count <= count - 1'd1;
|
||||
|
||||
//Wrapping
|
||||
if(count == 0 && !UP)
|
||||
count <= COUNT_TO;
|
||||
if(count == 14'h3fff && UP)
|
||||
count <= COUNT_TO;
|
||||
|
||||
//Resets
|
||||
if(RST) begin
|
||||
if(RESET_VALUE == "ZERO")
|
||||
count <= 0;
|
||||
else
|
||||
count <= COUNT_TO;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
"FALLING": begin
|
||||
always @(posedge CLK, negedge RST) begin
|
||||
|
||||
//Main counter
|
||||
if(KEEP) begin
|
||||
end
|
||||
else if(UP)
|
||||
count <= count + 1'd1;
|
||||
else
|
||||
count <= count - 1'd1;
|
||||
|
||||
//Wrapping
|
||||
if(count == 0 && !UP)
|
||||
count <= COUNT_TO;
|
||||
if(count == 14'h3fff && UP)
|
||||
count <= COUNT_TO;
|
||||
|
||||
//Resets
|
||||
if(!RST) begin
|
||||
if(RESET_VALUE == "ZERO")
|
||||
count <= 0;
|
||||
else
|
||||
count <= COUNT_TO;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
"BOTH": begin
|
||||
initial begin
|
||||
$display("Both-edge reset mode for GP_COUNT14_ADV not implemented");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
"LEVEL": begin
|
||||
always @(posedge CLK, posedge RST) begin
|
||||
|
||||
//Resets
|
||||
if(RST) begin
|
||||
if(RESET_VALUE == "ZERO")
|
||||
count <= 0;
|
||||
else
|
||||
count <= COUNT_TO;
|
||||
end
|
||||
|
||||
else begin
|
||||
|
||||
//Main counter
|
||||
if(KEEP) begin
|
||||
end
|
||||
else if(UP)
|
||||
count <= count + 1'd1;
|
||||
else
|
||||
count <= count - 1'd1;
|
||||
|
||||
//Wrapping
|
||||
if(count == 0 && !UP)
|
||||
count <= COUNT_TO;
|
||||
if(count == 14'h3fff && UP)
|
||||
count <= COUNT_TO;
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
default: begin
|
||||
initial begin
|
||||
$display("Invalid RESET_MODE on GP_COUNT14_ADV");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endcase
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
|
||||
input UP, input KEEP, output reg[7:0] POUT);
|
||||
|
||||
parameter RESET_MODE = "RISING";
|
||||
parameter RESET_VALUE = "ZERO";
|
||||
|
||||
parameter COUNT_TO = 8'h1;
|
||||
parameter CLKIN_DIVIDE = 1;
|
||||
|
||||
reg[7:0] count = COUNT_TO;
|
||||
|
||||
initial begin
|
||||
if(CLKIN_DIVIDE != 1) begin
|
||||
$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
//Combinatorially output underflow flag whenever we wrap low
|
||||
always @(*) begin
|
||||
if(UP)
|
||||
OUT <= (count == 8'hff);
|
||||
else
|
||||
OUT <= (count == 8'h0);
|
||||
POUT <= count;
|
||||
end
|
||||
|
||||
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
|
||||
//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
|
||||
generate
|
||||
case(RESET_MODE)
|
||||
|
||||
"RISING": begin
|
||||
always @(posedge CLK, posedge RST) begin
|
||||
|
||||
//Main counter
|
||||
if(KEEP) begin
|
||||
end
|
||||
else if(UP)
|
||||
count <= count + 1'd1;
|
||||
else
|
||||
count <= count - 1'd1;
|
||||
|
||||
//Wrapping
|
||||
if(count == 0 && !UP)
|
||||
count <= COUNT_TO;
|
||||
if(count == 8'hff && UP)
|
||||
count <= COUNT_TO;
|
||||
|
||||
//Resets
|
||||
if(RST) begin
|
||||
if(RESET_VALUE == "ZERO")
|
||||
count <= 0;
|
||||
else
|
||||
count <= COUNT_TO;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
"FALLING": begin
|
||||
always @(posedge CLK, negedge RST) begin
|
||||
|
||||
//Main counter
|
||||
if(KEEP) begin
|
||||
end
|
||||
else if(UP)
|
||||
count <= count + 1'd1;
|
||||
else
|
||||
count <= count - 1'd1;
|
||||
|
||||
//Wrapping
|
||||
if(count == 0 && !UP)
|
||||
count <= COUNT_TO;
|
||||
if(count == 8'hff && UP)
|
||||
count <= COUNT_TO;
|
||||
|
||||
//Resets
|
||||
if(!RST) begin
|
||||
if(RESET_VALUE == "ZERO")
|
||||
count <= 0;
|
||||
else
|
||||
count <= COUNT_TO;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
"BOTH": begin
|
||||
initial begin
|
||||
$display("Both-edge reset mode for GP_COUNT8_ADV not implemented");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
"LEVEL": begin
|
||||
always @(posedge CLK, posedge RST) begin
|
||||
|
||||
//Resets
|
||||
if(RST) begin
|
||||
if(RESET_VALUE == "ZERO")
|
||||
count <= 0;
|
||||
else
|
||||
count <= COUNT_TO;
|
||||
end
|
||||
|
||||
else begin
|
||||
|
||||
//Main counter
|
||||
if(KEEP) begin
|
||||
end
|
||||
else if(UP)
|
||||
count <= count + 1'd1;
|
||||
else
|
||||
count <= count - 1'd1;
|
||||
|
||||
//Wrapping
|
||||
if(count == 0 && !UP)
|
||||
count <= COUNT_TO;
|
||||
if(count == 8'hff && UP)
|
||||
count <= COUNT_TO;
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
default: begin
|
||||
initial begin
|
||||
$display("Invalid RESET_MODE on GP_COUNT8_ADV");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endcase
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
module GP_COUNT8(
|
||||
input wire CLK,
|
||||
input wire RST,
|
||||
output reg OUT,
|
||||
output reg[7:0] POUT);
|
||||
|
||||
parameter RESET_MODE = "RISING";
|
||||
|
||||
parameter COUNT_TO = 8'h1;
|
||||
parameter CLKIN_DIVIDE = 1;
|
||||
|
||||
initial begin
|
||||
if(CLKIN_DIVIDE != 1) begin
|
||||
$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
reg[7:0] count = COUNT_TO;
|
||||
|
||||
//Combinatorially output underflow flag whenever we wrap low
|
||||
always @(*) begin
|
||||
OUT <= (count == 8'h0);
|
||||
POUT <= count;
|
||||
end
|
||||
|
||||
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
|
||||
//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
|
||||
generate
|
||||
case(RESET_MODE)
|
||||
|
||||
"RISING": begin
|
||||
always @(posedge CLK, posedge RST) begin
|
||||
count <= count - 1'd1;
|
||||
if(count == 0)
|
||||
count <= COUNT_TO;
|
||||
|
||||
if(RST)
|
||||
count <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
"FALLING": begin
|
||||
always @(posedge CLK, negedge RST) begin
|
||||
count <= count - 1'd1;
|
||||
if(count == 0)
|
||||
count <= COUNT_TO;
|
||||
|
||||
if(!RST)
|
||||
count <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
"BOTH": begin
|
||||
initial begin
|
||||
$display("Both-edge reset mode for GP_COUNT8 not implemented");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
"LEVEL": begin
|
||||
always @(posedge CLK, posedge RST) begin
|
||||
if(RST)
|
||||
count <= 0;
|
||||
|
||||
else begin
|
||||
count <= count - 1'd1;
|
||||
if(count == 0)
|
||||
count <= COUNT_TO;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
default: begin
|
||||
initial begin
|
||||
$display("Invalid RESET_MODE on GP_COUNT8");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endcase
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
module GP_DCMPREF(output reg[7:0]OUT);
|
||||
parameter[7:0] REF_VAL = 8'h00;
|
||||
initial OUT = REF_VAL;
|
||||
endmodule
|
||||
|
||||
module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
|
||||
|
||||
always @(*) begin
|
||||
case(SEL)
|
||||
2'd00: begin
|
||||
OUTA <= IN0;
|
||||
OUTB <= IN3;
|
||||
end
|
||||
|
||||
2'd01: begin
|
||||
OUTA <= IN1;
|
||||
OUTB <= IN2;
|
||||
end
|
||||
|
||||
2'd02: begin
|
||||
OUTA <= IN2;
|
||||
OUTB <= IN1;
|
||||
end
|
||||
|
||||
2'd03: begin
|
||||
OUTA <= IN3;
|
||||
OUTB <= IN0;
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
||||
module GP_DELAY(input IN, output reg OUT);
|
||||
|
||||
parameter DELAY_STEPS = 1;
|
||||
parameter GLITCH_FILTER = 0;
|
||||
|
||||
initial OUT = 0;
|
||||
|
||||
generate
|
||||
|
||||
if(GLITCH_FILTER) begin
|
||||
initial begin
|
||||
$display("ERROR: GP_DELAY glitch filter mode not implemented");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
//TODO: These delays are PTV dependent! For now, hard code 3v3 timing
|
||||
//Change simulation-mode delay depending on global Vdd range (how to specify this?)
|
||||
always @(*) begin
|
||||
case(DELAY_STEPS)
|
||||
1: #166 OUT = IN;
|
||||
2: #318 OUT = IN;
|
||||
2: #471 OUT = IN;
|
||||
3: #622 OUT = IN;
|
||||
default: begin
|
||||
$display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
|
||||
$finish;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
module GP_DFF(input D, CLK, output reg Q);
|
||||
parameter [0:0] INIT = 1'bx;
|
||||
initial Q = INIT;
|
||||
always @(posedge CLK) begin
|
||||
Q <= D;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module GP_DFFI(input D, CLK, output reg nQ);
|
||||
parameter [0:0] INIT = 1'bx;
|
||||
initial nQ = INIT;
|
||||
always @(posedge CLK) begin
|
||||
nQ <= ~D;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module GP_DFFR(input D, CLK, nRST, output reg Q);
|
||||
parameter [0:0] INIT = 1'bx;
|
||||
initial Q = INIT;
|
||||
always @(posedge CLK, negedge nRST) begin
|
||||
if (!nRST)
|
||||
Q <= 1'b0;
|
||||
else
|
||||
Q <= D;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module GP_DFFRI(input D, CLK, nRST, output reg nQ);
|
||||
parameter [0:0] INIT = 1'bx;
|
||||
initial nQ = INIT;
|
||||
always @(posedge CLK, negedge nRST) begin
|
||||
if (!nRST)
|
||||
nQ <= 1'b1;
|
||||
else
|
||||
nQ <= ~D;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module GP_DFFS(input D, CLK, nSET, output reg Q);
|
||||
parameter [0:0] INIT = 1'bx;
|
||||
initial Q = INIT;
|
||||
always @(posedge CLK, negedge nSET) begin
|
||||
if (!nSET)
|
||||
Q <= 1'b1;
|
||||
else
|
||||
Q <= D;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module GP_DFFSI(input D, CLK, nSET, output reg nQ);
|
||||
parameter [0:0] INIT = 1'bx;
|
||||
initial nQ = INIT;
|
||||
always @(posedge CLK, negedge nSET) begin
|
||||
if (!nSET)
|
||||
nQ <= 1'b0;
|
||||
else
|
||||
nQ <= ~D;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module GP_DFFSR(input D, CLK, nSR, output reg Q);
|
||||
parameter [0:0] INIT = 1'bx;
|
||||
parameter [0:0] SRMODE = 1'bx;
|
||||
initial Q = INIT;
|
||||
always @(posedge CLK, negedge nSR) begin
|
||||
if (!nSR)
|
||||
Q <= SRMODE;
|
||||
else
|
||||
Q <= D;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
|
||||
parameter [0:0] INIT = 1'bx;
|
||||
parameter [0:0] SRMODE = 1'bx;
|
||||
initial nQ = INIT;
|
||||
always @(posedge CLK, negedge nSR) begin
|
||||
if (!nSR)
|
||||
nQ <= ~SRMODE;
|
||||
else
|
||||
nQ <= ~D;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module GP_DLATCH(input D, input nCLK, output reg Q);
|
||||
parameter [0:0] INIT = 1'bx;
|
||||
initial Q = INIT;
|
||||
always @(*) begin
|
||||
if(!nCLK)
|
||||
Q <= D;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module GP_DLATCHI(input D, input nCLK, output reg nQ);
|
||||
parameter [0:0] INIT = 1'bx;
|
||||
initial nQ = INIT;
|
||||
always @(*) begin
|
||||
if(!nCLK)
|
||||
nQ <= ~D;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
|
||||
parameter [0:0] INIT = 1'bx;
|
||||
initial Q = INIT;
|
||||
always @(*) begin
|
||||
if(!nRST)
|
||||
Q <= 1'b0;
|
||||
else if(!nCLK)
|
||||
Q <= D;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
|
||||
parameter [0:0] INIT = 1'bx;
|
||||
initial nQ = INIT;
|
||||
always @(*) begin
|
||||
if(!nRST)
|
||||
nQ <= 1'b1;
|
||||
else if(!nCLK)
|
||||
nQ <= ~D;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
|
||||
parameter [0:0] INIT = 1'bx;
|
||||
initial Q = INIT;
|
||||
always @(*) begin
|
||||
if(!nSET)
|
||||
Q <= 1'b1;
|
||||
else if(!nCLK)
|
||||
Q <= D;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
|
||||
parameter [0:0] INIT = 1'bx;
|
||||
initial nQ = INIT;
|
||||
always @(*) begin
|
||||
if(!nSET)
|
||||
nQ <= 1'b0;
|
||||
else if(!nCLK)
|
||||
nQ <= ~D;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
|
||||
parameter [0:0] INIT = 1'bx;
|
||||
parameter[0:0] SRMODE = 1'bx;
|
||||
initial Q = INIT;
|
||||
always @(*) begin
|
||||
if(!nSR)
|
||||
Q <= SRMODE;
|
||||
else if(!nCLK)
|
||||
Q <= D;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
|
||||
parameter [0:0] INIT = 1'bx;
|
||||
parameter[0:0] SRMODE = 1'bx;
|
||||
initial nQ = INIT;
|
||||
always @(*) begin
|
||||
if(!nSR)
|
||||
nQ <= ~SRMODE;
|
||||
else if(!nCLK)
|
||||
nQ <= ~D;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module GP_IBUF(input IN, output OUT);
|
||||
assign OUT = IN;
|
||||
endmodule
|
||||
|
||||
module GP_IOBUF(input IN, input OE, output OUT, inout IO);
|
||||
assign OUT = IO;
|
||||
assign IO = OE ? IN : 1'bz;
|
||||
endmodule
|
||||
|
||||
module GP_INV(input IN, output OUT);
|
||||
assign OUT = ~IN;
|
||||
endmodule
|
||||
|
||||
module GP_OBUF(input IN, output OUT);
|
||||
assign OUT = IN;
|
||||
endmodule
|
||||
|
||||
module GP_OBUFT(input IN, input OE, output OUT);
|
||||
assign OUT = OE ? IN : 1'bz;
|
||||
endmodule
|
||||
|
||||
module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
|
||||
initial OUT = 0;
|
||||
parameter PATTERN_DATA = 16'h0;
|
||||
parameter PATTERN_LEN = 5'd16;
|
||||
|
||||
reg[3:0] count = 0;
|
||||
always @(posedge CLK) begin
|
||||
if(!nRST)
|
||||
OUT <= PATTERN_DATA[0];
|
||||
|
||||
else begin
|
||||
count <= count + 1;
|
||||
OUT <= PATTERN_DATA[count];
|
||||
|
||||
if( (count + 1) == PATTERN_LEN)
|
||||
count <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
|
||||
|
||||
parameter OUTA_TAP = 1;
|
||||
parameter OUTA_INVERT = 0;
|
||||
parameter OUTB_TAP = 1;
|
||||
|
||||
reg[15:0] shreg = 0;
|
||||
|
||||
always @(posedge CLK, negedge nRST) begin
|
||||
|
||||
if(!nRST)
|
||||
shreg = 0;
|
||||
|
||||
else
|
||||
shreg <= {shreg[14:0], IN};
|
||||
|
||||
end
|
||||
|
||||
assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
|
||||
assign OUTB = shreg[OUTB_TAP - 1];
|
||||
|
||||
endmodule
|
||||
|
||||
module GP_VDD(output OUT);
|
||||
assign OUT = 1;
|
||||
endmodule
|
||||
|
||||
module GP_VSS(output OUT);
|
||||
assign OUT = 0;
|
||||
endmodule
|
||||
Loading…
Reference in New Issue