mirror of https://github.com/YosysHQ/yosys.git
Added blackbox $__COUNT_ cell model
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@ -2,6 +2,7 @@
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OBJS += techlibs/greenpak4/synth_greenpak4.o
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OBJS += techlibs/greenpak4/greenpak4_dffinv.o
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$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_blackbox.v))
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$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_latch.v))
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$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_map.v))
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$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim.v))
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module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
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input wire CE;
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input wire CLK;
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output reg OUT;
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output reg[WIDTH-1:0] POUT;
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input wire RST;
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input wire UP;
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parameter COUNT_TO = 1;
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parameter RESET_MODE = "RISING";
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parameter HAS_POUT = 0;
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parameter HAS_CE = 0;
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parameter WIDTH = 8;
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parameter DIRECTION = "DOWN";
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endmodule
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