mirror of https://github.com/YosysHQ/yosys.git
Add flops as blackboxes
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@ -40,3 +40,23 @@ RAM64X1D 4 0 15 2
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RAM128X1D 5 0 17 2
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- - - - - - - - 314 314 314 314 314 314 292 - -
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347 347 347 347 347 347 296 - - - - - - - - - -
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# Inputs: C CE D R
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# Outputs: Q
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FDRE 6 0 4 1
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- - - -
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# Inputs: C CE D S
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# Outputs: Q
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FDSE 7 0 4 1
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- - - -
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# Inputs: C CE CLR D
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# Outputs: Q
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FDCE 8 0 4 1
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- - 404 -
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# Inputs: C CE D PRE
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# Outputs: Q
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FDPE 9 0 4 1
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- - - 404
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@ -38,5 +38,12 @@ module \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPL
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module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
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module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
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`ifndef DEPRECATED
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module FDRE_1 (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; FDRE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .R(R), .Q(Q)); endmodule
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module FDSE_1 (output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b0; FDSE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .S(S), .Q(Q)); endmodule
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module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; FDCE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .CLR(CLR), .Q(Q)); endmodule
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module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; FDPE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .PRE(PRE), .Q(Q)); endmodule
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`endif
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`endif
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