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Merge pull request #777 from mmicko/achronix_cell_sim_fix 

Fix cells_sim.v for Achronix FPGA
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Clifford Wolf 2019-01-04 15:18:18 +01:00 committed by GitHub
parent 6d1e7e9403 50ef4561d4
commit e041ae3c6d
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techlibs/achronix/speedster22i/cells_sim.v
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@ -61,7 +61,7 @@ reg [1:0] s1;
end
endfunction
always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
always @(dataa_w or datab_w or datac_w or datad_w) begin
combout_rt = lut_data(lut_function, dataa_w, datab_w,
datac_w, datad_w);
end