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Remove #ifndef ABC

This commit is contained in:
Eddie Hung 2019-06-11 12:02:31 -07:00
parent a138381ac3
commit 8a708d1fdb
1 changed files with 0 additions and 4 deletions
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4
techlibs/xilinx/cells_sim.v
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@ -295,10 +295,8 @@ module RAM64X1D (
reg [63:0] mem = INIT;
assign SPO = mem[a];
assign DPO = mem[dpra];
`ifndef _ABC
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[a] <= D;
`endif
endmodule
(* abc_box_id = 5 /*, lib_whitebox*/ *)
@ -312,10 +310,8 @@ module RAM128X1D (
reg [127:0] mem = INIT;
assign SPO = mem[A];
assign DPO = mem[DPRA];
`ifndef _ABC
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[A] <= D;
`endif
endmodule
module SRL16E (