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Cleanup synth_xilinx

This commit is contained in:
Eddie Hung 2019-03-15 23:01:40 -07:00
parent 06f8f2654a
commit 29a8d4745e
2 changed files with 2 additions and 3 deletions
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2
techlibs/xilinx/cells_map.v
View File

@ -95,7 +95,7 @@ module \$__SHREG_ (input C, input D, input [31:0] L, input E, output Q);
MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6]));
end
end
else if (DEPTH < 129 || (DEPTH <= 129 && &_TECHMAP_CONSTMSK_L_)) begin
else if (DEPTH <= 128 || (DEPTH == 129 && &_TECHMAP_CONSTMSK_L_)) begin
// Handle cases where depth is just 1 over a convenient value,
if (&_TECHMAP_CONSTMSK_L_) begin
// For constant length, use the flop

3
techlibs/xilinx/synth_xilinx.cc
View File

@ -110,6 +110,7 @@ struct SynthXilinxPass : public Pass
log(" dffsr2dff\n");
log(" dff2dffe\n");
log(" opt -full\n");
log(" simplemap t:$dff*\n");
log(" shregmap -tech xilinx\n");
log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v +/xilinx/ff_map.v\n");
log(" opt -fast\n");
@ -257,8 +258,6 @@ struct SynthXilinxPass : public Pass
Pass::call(design, "simplemap t:$dff*");
Pass::call(design, "shregmap -tech xilinx");
Pass::call(design, "techmap -map +/xilinx/cells_map.v t:$__SHREG_");
Pass::call(design, "opt -fast");
if (vpr) {
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY");