mirror of https://github.com/YosysHQ/yosys.git
synth_ice40 to have new -abc9 arg
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c7ef3863f3
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@ -89,13 +89,16 @@ struct SynthIce40Pass : public ScriptPass
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log(" generate an output netlist (and BLIF file) suitable for VPR\n");
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log(" (this feature is experimental and incomplete)\n");
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log("\n");
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log(" -abc9\n");
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log(" use abc9 instead of abc\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_opt, blif_file, edif_file, json_file;
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string top_opt, blif_file, edif_file, json_file, abc;
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bool nocarry, nodffe, nobram, flatten, retime, relut, noabc, abc2, vpr;
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int min_ce_use;
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@ -115,6 +118,7 @@ struct SynthIce40Pass : public ScriptPass
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noabc = false;
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abc2 = false;
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vpr = false;
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abc = "abc";
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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@ -193,6 +197,10 @@ struct SynthIce40Pass : public ScriptPass
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vpr = true;
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continue;
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}
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if (args[argidx] == "-abc9") {
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abc = "abc9";
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -249,7 +257,7 @@ struct SynthIce40Pass : public ScriptPass
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else
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run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
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if (retime || help_mode)
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run("abc -dff", "(only if -retime)");
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run(abc + " -dff", "(only if -retime)");
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run("ice40_opt");
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}
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@ -273,7 +281,7 @@ struct SynthIce40Pass : public ScriptPass
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if (check_label("map_luts"))
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{
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if (abc2 || help_mode) {
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run("abc", " (only if -abc2)");
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run(abc, " (only if -abc2)");
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run("ice40_opt", "(only if -abc2)");
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}
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run("techmap -map +/ice40/latches_map.v");
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@ -282,7 +290,7 @@ struct SynthIce40Pass : public ScriptPass
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run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
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}
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if (!noabc) {
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run("abc -lut 4", "(skip if -noabc)");
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run(abc + " -lut 4", "(skip if -noabc)");
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}
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run("clean");
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if (relut || help_mode) {
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