mirror of https://github.com/YosysHQ/yosys.git
Tidy up, fix for -nosrl
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726e2da8f2
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@ -22,21 +22,26 @@
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`ifndef _NO_FFS
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`ifndef _NO_POS_SR
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module \$_DFF_N_ (input D, C, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
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module \$_DFF_P_ (input D, C, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
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module \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
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module \$_DFFE_PP_ (input D, C, E, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
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module \$_DFF_NN0_ (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
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module \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
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module \$_DFF_PN0_ (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
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module \$_DFF_PP0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
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module \$_DFF_NN1_ (input D, C, R, output Q); \$_DFF_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
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module \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
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module \$_DFF_PN1_ (input D, C, R, output Q); \$_DFF_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
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module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
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`endif
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module \$_DFF_NN0_ (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
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module \$_DFF_PN0_ (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
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module \$_DFF_NN1_ (input D, C, R, output Q); \$_DFF_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
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module \$_DFF_PN1_ (input D, C, R, output Q); \$_DFF_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
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`endif
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`endif
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@ -116,8 +116,7 @@ struct SynthXilinxPass : public Pass
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log(" pmux2shiftx (without '-nosrl' only)\n");
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log(" opt_expr -mux_undef (without '-nosrl' only)\n");
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log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
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log(" opt -full\n");
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log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
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log(" techmap -map +/xilinx/arith_map.v\n");
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log(" opt -fast\n");
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log("\n");
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log(" map_cells:\n");
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@ -125,7 +124,8 @@ struct SynthXilinxPass : public Pass
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log(" clean\n");
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log("\n");
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log(" map_luts:\n");
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log(" techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n");
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log(" opt -full\n");
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log(" techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v\n");
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log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n");
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log(" clean\n");
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log(" shregmap -minlen 3 -init -params -enpol any_or_none (without '-nosrl' only)\n");
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@ -282,12 +282,10 @@ struct SynthXilinxPass : public Pass
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Pass::call(design, "shregmap -tech xilinx -minlen 3");
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}
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Pass::call(design, "opt -full");
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if (vpr) {
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Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
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Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
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} else {
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Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
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Pass::call(design, "techmap -map +/xilinx/arith_map.v");
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}
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Pass::call(design, "hierarchy -check");
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@ -302,7 +300,8 @@ struct SynthXilinxPass : public Pass
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if (check_label(active, run_from, run_to, "map_luts"))
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{
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Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?");
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Pass::call(design, "opt -full");
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Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v");
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Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
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Pass::call(design, "clean");
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if (!nosrl)
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