mirror of https://github.com/YosysHQ/yosys.git
Merge branch 'map_cells_before_map_luts' into xc7srl
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commit
726e2da8f2
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@ -121,7 +121,7 @@ struct SynthXilinxPass : public Pass
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log(" opt -fast\n");
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log("\n");
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log(" map_cells:\n");
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log(" techmap -map +/techmap.v -map +/xilinx/cells_map.v\n");
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log(" techmap -map +/xilinx/cells_map.v\n");
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log(" clean\n");
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log("\n");
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log(" map_luts:\n");
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@ -296,7 +296,7 @@ struct SynthXilinxPass : public Pass
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if (check_label(active, run_from, run_to, "map_cells"))
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{
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Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/cells_map.v");
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Pass::call(design, "techmap -map +/xilinx/cells_map.v");
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Pass::call(design, "clean");
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}
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