mirror of https://github.com/YosysHQ/yosys.git
Re-added clean after techmap in synth_xilinx
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -124,6 +124,7 @@ struct SynthXilinxPass : public Pass
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log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
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log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n");
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log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
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log(" clean\n");
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log("\n");
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log(" check:\n");
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log(" hierarchy -check\n");
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@ -280,6 +281,7 @@ struct SynthXilinxPass : public Pass
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Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
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Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
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"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
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Pass::call(design, "clean");
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}
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if (check_label(active, run_from, run_to, "check"))
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