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Apparently, this reduces number of MUXCY/XORCY

This commit is contained in:
Eddie Hung 2019-04-26 16:28:48 -07:00
parent e31e21766d
commit ccc283737d
1 changed files with 9 additions and 10 deletions
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19
techlibs/xilinx/synth_xilinx.cc
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@ -287,11 +287,18 @@ struct SynthXilinxPass : public Pass
if (check_label(active, run_from, run_to, "fine"))
{
Pass::call(design, "opt -fast");
Pass::call(design, "opt -fast -full");
Pass::call(design, "memory_map");
Pass::call(design, "dffsr2dff");
Pass::call(design, "dff2dffe");
if (!nocarry) {
if (vpr)
Pass::call(design, "techmap -D _EXPLICIT_CARRY -map +/xilinx/arith_map.v");
else
Pass::call(design, "techmap -map +/xilinx/arith_map.v");
}
// shregmap -tech xilinx can cope with $shiftx and $mux
// cells for identifying variable-length shift registers,
// so attempt to convert $pmux-es to the former
@ -300,15 +307,7 @@ struct SynthXilinxPass : public Pass
Pass::call(design, "pmux2shiftx");
Pass::call(design, "opt -full");
if (!nocarry) {
if (vpr)
Pass::call(design, "techmap -map +/techmap.v -D _EXPLICIT_CARRY -map +/xilinx/arith_map.v");
else
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
}
else {
Pass::call(design, "techmap");
}
Pass::call(design, "techmap");
Pass::call(design, "opt -fast");
// shregmap with '-tech xilinx' infers variable length shift regs