mirror of https://github.com/YosysHQ/yosys.git
coolrunner2: Add extraction for TFFs
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@ -4,4 +4,5 @@ OBJS += techlibs/coolrunner2/coolrunner2_sop.o
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$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_latch.v))
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$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_sim.v))
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$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/tff_extract.v))
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$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/xc2_dff.lib))
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@ -149,6 +149,16 @@ struct SynthCoolrunner2Pass : public ScriptPass
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run("dfflibmap -prepare -liberty +/coolrunner2/xc2_dff.lib");
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}
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if (check_label("map_tff"))
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{
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// This is quite hacky. By telling abc that it can only use AND and XOR gates, abc will try and use XOR
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// gates "whenever possible." This will hopefully cause toggle flip-flop structures to turn into an XOR
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// connected to a D flip-flop. We then match on these and convert them into XC2 TFF cells.
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run("abc -g AND,XOR");
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run("clean");
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run("extract -map +/coolrunner2/tff_extract.v");
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}
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if (check_label("map_pla"))
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{
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run("abc -sop -I 40 -P 56");
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@ -160,6 +170,8 @@ struct SynthCoolrunner2Pass : public ScriptPass
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run("dfflibmap -liberty +/coolrunner2/xc2_dff.lib");
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run("dffinit -ff FDCP Q INIT");
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run("dffinit -ff FDCP_N Q INIT");
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run("dffinit -ff FTCP Q INIT");
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run("dffinit -ff FTCP_N Q INIT");
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run("dffinit -ff LDCP Q INIT");
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run("dffinit -ff LDCP_N Q INIT");
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run("coolrunner2_sop");
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@ -0,0 +1,41 @@
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module FTCP (C, PRE, CLR, T, Q);
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input C, PRE, CLR, T;
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output wire Q;
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wire xorout;
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$_XOR_ xorgate (
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.A(T),
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.B(Q),
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.Y(xorout),
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);
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$_DFFSR_PPP_ dff (
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.C(C),
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.D(xorout),
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.Q(Q),
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.S(PRE),
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.R(CLR),
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);
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endmodule
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module FTCP_N (C, PRE, CLR, T, Q);
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input C, PRE, CLR, T;
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output wire Q;
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wire xorout;
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$_XOR_ xorgate (
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.A(T),
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.B(Q),
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.Y(xorout),
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);
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$_DFFSR_NPP_ dff (
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.C(C),
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.D(xorout),
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.Q(Q),
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.S(PRE),
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.R(CLR),
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);
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endmodule
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