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Merge branch 'master' of https://github.com/cliffordwolf/yosys into counter-extraction

This commit is contained in:
Andrew Zonenberg 2017-08-30 16:40:41 -07:00
parent 634f18be96 c0034f51e6
commit 06754108fc
3 changed files with 56 additions and 36 deletions
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16
kernel/rtlil.cc
View File

@ -234,6 +234,22 @@ pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
return data;
}
void RTLIL::AttrObject::set_src_attribute(const std::string &src)
{
if (src.empty())
attributes.erase("\\src");
else
attributes["\\src"] = src;
}
std::string RTLIL::AttrObject::get_src_attribute() const
{
std::string src;
if (attributes.count("\\src"))
src = attributes.at("\\src").decode_string();
return src;
}
bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
{
if (full_selection)

4
kernel/rtlil.h
View File

@ -505,9 +505,13 @@ struct RTLIL::AttrObject
void set_bool_attribute(RTLIL::IdString id);
bool get_bool_attribute(RTLIL::IdString id) const;
void set_strpool_attribute(RTLIL::IdString id, const pool<string> &data);
void add_strpool_attribute(RTLIL::IdString id, const pool<string> &data);
pool<string> get_strpool_attribute(RTLIL::IdString id) const;
void set_src_attribute(const std::string &src);
std::string get_src_attribute() const;
};
struct RTLIL::SigChunk

72
techlibs/greenpak4/cells_sim_digital.v
View File

@ -147,7 +147,15 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
"RISING": begin
always @(posedge CLK, posedge RST) begin
if(KEEP) begin
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
@ -161,21 +169,21 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO;
end
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
end
end
"FALLING": begin
always @(posedge CLK, negedge RST) begin
if(KEEP) begin
//Resets
if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
@ -189,14 +197,6 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO;
end
//Resets
if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
end
end
@ -286,8 +286,16 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
"RISING": begin
always @(posedge CLK, posedge RST) begin
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
//Main counter
if(KEEP) begin
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
@ -301,22 +309,22 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO;
end
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
end
end
"FALLING": begin
always @(posedge CLK, negedge RST) begin
//Resets
if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
//Main counter
if(KEEP) begin
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
@ -330,14 +338,6 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO;
end
//Resets
if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
end
end