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Improve $specrule interface 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-04-23 22:18:04 +02:00
parent 71c38d9de5
commit 4575e4ad86
3 changed files with 24 additions and 24 deletions
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38
frontends/verilog/verilog_parser.y
View File

@ -817,12 +817,7 @@ specify_item:
delete timing;
} |
TOK_ID '(' specify_edge expr specify_condition ',' specify_edge expr specify_condition ',' expr ')' ';' {
bool limit_gt = false;
if (*$1 == "$setup" || *$1 == "$hold")
limit_gt = true;
else if (*$1 == "$skew")
limit_gt = false;
else
if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$skew")
frontend_verilog_yyerror("Unsupported specify rule type: %s\n", $1->c_str());
AstNode *src_pen = AstNode::mkconst_int($3 != 0, false, 1);
@ -841,11 +836,14 @@ specify_item:
cell->children.push_back(new AstNode(AST_CELLTYPE));
cell->children.back()->str = "$specrule";
cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
cell->children.back()->str = "\\SRC_EN";
cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(*$1 == "$skew", false, 1)));
cell->children.back()->str = "\\SKEW";
cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
cell->children.back()->str = "\\SRC";
cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(*$1 == "$hold", false, 1)));
cell->children.back()->str = "\\HOLD";
cell->children.push_back(new AstNode(AST_PARASET, limit));
cell->children.back()->str = "\\T_LIMIT";
cell->children.push_back(new AstNode(AST_PARASET, src_pen));
cell->children.back()->str = "\\SRC_PEN";
@ -853,23 +851,23 @@ specify_item:
cell->children.push_back(new AstNode(AST_PARASET, src_pol));
cell->children.back()->str = "\\SRC_POL";
cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
cell->children.back()->str = "\\DST_EN";
cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
cell->children.back()->str = "\\DST";
cell->children.push_back(new AstNode(AST_PARASET, dst_pen));
cell->children.back()->str = "\\DST_PEN";
cell->children.push_back(new AstNode(AST_PARASET, dst_pol));
cell->children.back()->str = "\\DST_POL";
cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_int(limit_gt, false, 1)));
cell->children.back()->str = "\\LIMIT_GT";
cell->children.push_back(new AstNode(AST_ARGUMENT, src_en));
cell->children.back()->str = "\\SRC_EN";
cell->children.push_back(new AstNode(AST_PARASET, limit));
cell->children.back()->str = "\\T_LIMIT";
cell->children.push_back(new AstNode(AST_ARGUMENT, src_expr));
cell->children.back()->str = "\\SRC";
cell->children.push_back(new AstNode(AST_ARGUMENT, dst_en));
cell->children.back()->str = "\\DST_EN";
cell->children.push_back(new AstNode(AST_ARGUMENT, dst_expr));
cell->children.back()->str = "\\DST";
delete $1;
};

3
kernel/rtlil.cc
View File

@ -1223,7 +1223,8 @@ namespace {
param_bool("\\SRC_POL");
param_bool("\\DST_PEN");
param_bool("\\DST_POL");
param_bool("\\LIMIT_GT");
param_bool("\\SKEW");
param_bool("\\HOLD");
param("\\T_LIMIT");
port("\\SRC_EN", 1);
port("\\DST_EN", 1);

7
techlibs/common/simlib.v
View File

@ -1419,6 +1419,10 @@ endmodule
module \$specrule (EN_SRC, EN_DST, SRC, DST);
parameter SKEW = 0;
parameter HOLD = 0;
parameter T_LIMIT = 0;
parameter SRC_WIDTH = 1;
parameter DST_WIDTH = 1;
@ -1428,9 +1432,6 @@ parameter SRC_POL = 0;
parameter DST_PEN = 0;
parameter DST_POL = 0;
parameter LIMIT_GT = 0;
parameter T_LIMIT = 0;
input EN_SRC, EN_DST;
input [SRC_WIDTH-1:0] SRC;
input [DST_WIDTH-1:0] DST;