mirror of https://github.com/YosysHQ/yosys.git
Change synth_xilinx's -nomux to -minmuxf <int>
This commit is contained in:
Eddie Hung
parent
d54dceb547
commit
36e6da5396
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@ -155,6 +155,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
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endgenerate
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endmodule
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`ifdef MIN_MUX_INPUTS
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module \$__XILINX_SHIFTX (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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@ -207,10 +208,10 @@ module \$__XILINX_SHIFTX (A, B, Y);
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localparam B_WIDTH_new = $clog2(A_WIDTH_new);
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\$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y));
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end
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else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
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else if (A_WIDTH < `MIN_MUX_INPUTS) begin
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wire _TECHMAP_FAIL_ = 1;
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end
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else if (B_WIDTH == 3) begin
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else if (A_WIDTH <= 2 ** 3) begin
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localparam a_width0 = 2 ** 2;
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localparam a_widthN = A_WIDTH - a_width0;
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wire T0, T1;
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@ -219,47 +220,61 @@ module \$__XILINX_SHIFTX (A, B, Y);
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
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else
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assign T1 = A[A_WIDTH-1];
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MUXF7 fpga_hard_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
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MUXF7 fpga_hard_mux (.I0(T0), .I1(T1), .S(B[2]), .O(Y));
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end
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else if (B_WIDTH == 4) begin
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else if (A_WIDTH <= 2 ** 4) begin
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localparam a_width0 = 2 ** 2;
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localparam num_mux8 = A_WIDTH / a_width0;
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localparam a_widthN = A_WIDTH - num_mux8*a_width0;
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wire [4-1:0] T;
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for (i = 0; i < 4; i++)
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for (i = 0; i < num_mux8; i++)
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if (i < num_mux8)
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i]));
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else if (i == num_mux8 && a_widthN > 0) begin
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if (a_widthN > 1)
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
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else
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assign T[i] = A[A_WIDTH-1];
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end
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i]));
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if (a_widthN > 0) begin
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if (a_widthN > 1)
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1:num_mux8*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[num_mux8]));
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else
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assign T[i] = 1'bx;
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assign T[num_mux8] = A[A_WIDTH-1];
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end
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else
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assign T[num_mux8] = 1'bx;
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\$__XILINX_MUXF78 fpga_hard_mux (.I0(T[0]), .I1(T[1]), .I2(T[2]), .I3(T[3]), .S0(B[2]), .S1(B[3]), .O(Y));
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end
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else begin
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localparam a_width0 = 2 ** 4;
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localparam num_mux16 = A_WIDTH / a_width0;
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localparam a_widthN = A_WIDTH - num_mux16*a_width0;
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wire [(2**(B_WIDTH-4))-1:0] T;
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for (i = 0; i < 2 ** (B_WIDTH-4); i++)
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if (i < num_mux16)
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\$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
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else if (i == num_mux16 && a_widthN > 0) begin
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if (a_widthN > 1)
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\$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
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else
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assign T[i] = A[A_WIDTH-1];
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end
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wire [num_mux16-1:0] T;
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for (i = 0; i < num_mux16; i++)
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\$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
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if (a_widthN > 0) begin
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if (a_widthN > 1)
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\$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:num_mux16*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[num_mux16]));
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else
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assign T[i] = 1'bx;
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assign T[num_mux16] = A[A_WIDTH-1];
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end
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else
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assign T[num_mux16] = 1'bx;
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\$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
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end
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endgenerate
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endmodule
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(* techmap_celltype = "$__XILINX_SHIFTX" *)
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module _90__XILINX_SHIFTX (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
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endmodule
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module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
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input A, B, C, D, E, F, G, H, S, T, U;
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output Y;
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@ -271,6 +286,7 @@ input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
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output Y;
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\$__XILINX_SHIFTX #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
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endmodule
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`endif
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`ifndef _ABC
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module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
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@ -54,7 +54,7 @@ module \$shiftx (A, B, Y);
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wire _TECHMAP_FAIL_ = 1;
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end
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else begin
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if (B_WIDTH < 3 || A_WIDTH <= 4)
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if (((A_WIDTH + Y_WIDTH - 1) / Y_WIDTH) < `MIN_MUX_INPUTS)
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wire _TECHMAP_FAIL_ = 1;
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else
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\$__XILINX_SHIFTX #(
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@ -73,8 +73,10 @@ struct SynthXilinxPass : public ScriptPass
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log(" -nosrl\n");
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log(" disable inference of shift registers\n");
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log("\n");
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log(" -nomux\n");
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log(" disable inference of wide multiplexers\n");
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log(" -minmuxf <int>\n");
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log(" enable inference of hard multiplexer resources (MuxFx) for muxes at or\n");
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log(" above this number of inputs (minimum value 5).\n");
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log(" default: 0 (no inference)\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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@ -97,7 +99,8 @@ struct SynthXilinxPass : public ScriptPass
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}
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std::string top_opt, edif_file, blif_file, abc, arch;
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bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl, nomux;
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bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl;
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int minmuxf;
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void clear_flags() YS_OVERRIDE
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{
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@ -112,8 +115,8 @@ struct SynthXilinxPass : public ScriptPass
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nobram = false;
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nodram = false;
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nosrl = false;
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nomux = false;
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arch = "xc7";
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minmuxf = 0;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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@ -176,8 +179,8 @@ struct SynthXilinxPass : public ScriptPass
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nosrl = true;
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continue;
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}
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if (args[argidx] == "-nomux") {
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nomux = true;
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if (args[argidx] == "-minmuxf" && argidx+1 < args.size()) {
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minmuxf = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-abc9") {
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@ -191,6 +194,9 @@ struct SynthXilinxPass : public ScriptPass
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if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s")
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log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str());
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if (minmuxf != 0 && minmuxf < 5)
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log_cmd_error("-minmuxf value must be 0 or >= 5.\n");
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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@ -227,9 +233,9 @@ struct SynthXilinxPass : public ScriptPass
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run("check");
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run("opt");
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if (help_mode)
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run("wreduce [c:* t:$mux %d]", "(no selection if -nomux)");
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run("wreduce [c:* t:$mux %d]", "(selection for '-minmuxf' only)");
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else
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run("wreduce" + std::string(nomux ? "" : " c:* t:$mux %d"));
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run("wreduce" + std::string(minmuxf > 0 ? " c:* t:$mux %d" : ""));
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run("peepopt");
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run("opt_clean");
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run("alumacc");
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@ -240,15 +246,15 @@ struct SynthXilinxPass : public ScriptPass
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run("memory -nomap");
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run("opt_clean");
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if (!nomux || help_mode)
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run("muxpack", " (skip if '-nomux')");
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if (minmuxf > 0 || help_mode)
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run("muxpack", " ('-minmuxf' only)");
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// shregmap -tech xilinx can cope with $shiftx and $mux
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// cells for identifying variable-length shift registers,
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// so attempt to convert $pmux-es to the former
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// Also: wide multiplexer inference benefits from this too
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if (!(nosrl && nomux) || help_mode)
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run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')");
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if (!(nosrl && minmuxf == 0) || help_mode)
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run("pmux2shiftx", "(skip if '-nosrl' and '-minmuxf' < 5)");
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}
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if (check_label("bram", "(skip if '-nobram')")) {
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@ -270,12 +276,15 @@ struct SynthXilinxPass : public ScriptPass
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run("memory_map");
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run("dffsr2dff");
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run("dff2dffe");
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if (!nomux || help_mode) {
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run("simplemap t:$mux", " (skip if -nomux)");
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// NB: Cost of mux2 is 100; mux8 should cost between 3 and 4
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// of those so that 4:1 muxes and below are implemented
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// out of mux2s
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run("muxcover -mux8=350 -mux16=400 -dmux=0", "(skip if -nomux)");
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if (minmuxf > 0 || help_mode) {
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run("simplemap t:$mux", " ('-minmuxf' only)");
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if (minmuxf > 0 || help_mode) {
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// NB: Cost of mux2 is 100; mux8 should cost between 3 and 4
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// of those so that 4:1 muxes and below are implemented
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// out of mux2s
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std::string muxcover_args = " -dmux=0 -mux8=350 -mux16=400";
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run("muxcover " + muxcover_args, "('-minmuxf' only)");
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}
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}
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run("opt -full");
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@ -287,26 +296,29 @@ struct SynthXilinxPass : public ScriptPass
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run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
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}
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std::string techmap_files = " -map +/techmap.v";
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std::string techmap_args = " -map +/techmap.v";
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if (help_mode)
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techmap_files += " [-map +/xilinx/mux_map.v]";
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else if (!nomux)
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techmap_files += " -map +/xilinx/mux_map.v";
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techmap_args += " [-map +/xilinx/mux_map.v]";
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else if (minmuxf > 0)
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techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", minmuxf);
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if (help_mode)
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techmap_files += " [-map +/xilinx/arith_map.v]";
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techmap_args += " [-map +/xilinx/arith_map.v]";
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else if (!nocarry) {
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techmap_files += " -map +/xilinx/arith_map.v";
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techmap_args += " -map +/xilinx/arith_map.v";
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if (vpr)
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techmap_files += " -D _EXPLICIT_CARRY";
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techmap_args += " -D _EXPLICIT_CARRY";
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else if (abc == "abc9")
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techmap_files += " -D _CLB_CARRY";
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techmap_args += " -D _CLB_CARRY";
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}
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run("techmap " + techmap_files);
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run("techmap " + techmap_args);
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run("opt -fast");
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}
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if (check_label("map_cells")) {
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run("techmap -map +/techmap.v -D _ABC -map +/xilinx/cells_map.v");
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std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
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if (minmuxf > 0)
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techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", minmuxf);
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run("techmap " + techmap_args);
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run("clean");
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}
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