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Merge remote-tracking branch 'origin/xaig' into xc7mux

This commit is contained in:
Eddie Hung 2019-06-22 19:44:17 -07:00
parent bbf3ad90f5 6027549464
commit d54dceb547
9 changed files with 85 additions and 391 deletions
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9
CHANGELOG
View File

@ -18,16 +18,17 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "equiv_opt" pass
- Added "shregmap -tech xilinx"
- Added "read_aiger" frontend
- Added "shregmap -tech xilinx"
- Added "muxcover -mux{4,8,16}=<cost>"
- Added "muxcover -dmux=<cost>"
- Added "muxcover -nopartial"
- Added "muxpack" pass
- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
- Added "synth_xilinx -abc9" (experimental)
- Added "synth_ice40 -abc9" (experimental)
- Added "synth -abc9" (experimental)
- Added "muxpack" pass
- Extended "muxcover -mux{4,8,16}=<cost>"
- Fixed sign extension of unsized constants with 'bx and 'bz MSB
- "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
- "synth_xilinx" to now infer wide multiplexers (-nomux to disable)
- Fixed sign extension of unsized constants with 'bx and 'bz MSB
Yosys 0.7 .. Yosys 0.8

60
backends/aiger/xaiger.cc
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@ -309,38 +309,46 @@ struct XAigerWriter
if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) {
RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr;
RTLIL::Wire* last_in = nullptr, *last_out = nullptr;
for (const auto &port_name : box_module->ports) {
RTLIL::Wire* w = box_module->wire(port_name);
auto &ports = box_module->ports;
for (auto it = ports.begin(); it != ports.end(); ) {
RTLIL::Wire* w = box_module->wire(*it);
log_assert(w);
if (w->port_input) {
if (w->attributes.count("\\abc_carry_in")) {
log_assert(!carry_in);
carry_in = w;
}
log_assert(!last_in || last_in->port_id < w->port_id);
last_in = w;
if (w->port_input && w->attributes.count("\\abc_carry_in")) {
if (carry_in)
log_error("More than one port with attribute 'abc_carry_in' found in module '%s'\n", log_id(box_module));
carry_in = w;
it = ports.erase(it);
continue;
}
if (w->port_output) {
if (w->attributes.count("\\abc_carry_out")) {
log_assert(!carry_out);
carry_out = w;
}
log_assert(!last_out || last_out->port_id < w->port_id);
last_out = w;
if (w->port_output && w->attributes.count("\\abc_carry_out")) {
if (carry_out)
log_error("More than one port with attribute 'abc_carry_out' found in module '%s'\n", log_id(box_module));
carry_out = w;
it = ports.erase(it);
continue;
}
++it;
}
if (carry_in) {
log_assert(last_in);
std::swap(box_module->ports[carry_in->port_id-1], box_module->ports[last_in->port_id-1]);
std::swap(carry_in->port_id, last_in->port_id);
}
if (carry_out) {
log_assert(last_out);
std::swap(box_module->ports[carry_out->port_id-1], box_module->ports[last_out->port_id-1]);
std::swap(carry_out->port_id, last_out->port_id);
if (!carry_in)
log_error("Port with attribute 'abc_carry_in' not found in module '%s'\n", log_id(box_module));
if (!carry_out)
log_error("Port with attribute 'abc_carry_out' not found in module '%s'\n", log_id(box_module));
for (const auto port_name : ports) {
RTLIL::Wire* w = box_module->wire(port_name);
log_assert(w);
if (w->port_id > carry_in->port_id)
--w->port_id;
if (w->port_id > carry_out->port_id)
--w->port_id;
log_assert(w->port_input || w->port_output);
log_assert(ports[w->port_id-1] == w->name);
}
ports.push_back(carry_in->name);
carry_in->port_id = ports.size();
ports.push_back(carry_out->name);
carry_out->port_id = ports.size();
}
// Fully pad all unused input connections of this box cell with S0

6
techlibs/ecp5/abc_5g.box
View File

@ -1,5 +1,11 @@
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
# Box 1 : CCU2C (2xCARRY + 2xLUT4)
# Outputs: S0, S1, COUT
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
# name ID w/b ins outs
CCU2C 1 1 9 3

112
techlibs/ice40/abc_hx.box
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@ -1,113 +1,17 @@
# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
# Inputs: C D
# Outputs: Q
SB_DFF 1 0 2 1
- -
# Inputs: C D E
# Outputs: Q
SB_DFFE 2 0 3 1
- - -
# Inputs: C D R
# Outputs: Q
SB_DFFSR 3 0 3 1
- - -
# Inputs: C D R
# Outputs: Q
SB_DFFR 4 0 3 1
- - -
# Inputs: C D S
# Outputs: Q
SB_DFFSS 5 0 3 1
- - -
# Inputs: C D S
# Outputs: Q
SB_DFFS 6 0 3 1
- - -
# Inputs: C D E R
# Outputs: Q
SB_DFFESR 7 0 4 1
- - - -
# Inputs: C D E R
# Outputs: Q
SB_DFFER 8 0 4 1
- - - -
# Inputs: C D E S
# Outputs: Q
SB_DFFESS 9 0 4 1
- - - -
# Inputs: C D E S
# Outputs: Q
SB_DFFES 10 0 4 1
- - - -
# Inputs: C D
# Outputs: Q
SB_DFFN 11 0 2 1
- -
# Inputs: C D E
# Outputs: Q
SB_DFFNE 12 0 3 1
- - -
# Inputs: C D R
# Outputs: Q
SB_DFFNSR 13 0 3 1
- - -
# Inputs: C D R
# Outputs: Q
SB_DFFNR 14 0 3 1
- - -
# Inputs: C D S
# Outputs: Q
SB_DFFNSS 15 0 3 1
- - -
# Inputs: C D S
# Outputs: Q
SB_DFFNS 16 0 3 1
- - -
# Inputs: C D E R
# Outputs: Q
SB_DFFNESR 17 0 4 1
- - - -
# Inputs: C D E R
# Outputs: Q
SB_DFFNER 18 0 4 1
- - - -
# Inputs: C D E S
# Outputs: Q
SB_DFFNESS 19 0 4 1
- - - -
# Inputs: C D E S
# Outputs: Q
SB_DFFNES 20 0 4 1
- - - -
# Inputs: CI I0 I1
# Inputs: I0 I1 CI
# Outputs: CO
SB_CARRY 21 1 3 1
126 259 231
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
SB_CARRY 1 1 3 1
259 231 126
# Inputs: I0 I1 I2 I3
# Outputs: O
SB_LUT4 22 1 4 1
SB_LUT4 2 1 4 1
449 400 379 316

110
techlibs/ice40/abc_lp.box
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@ -1,113 +1,17 @@
# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
# NB: Inputs/Outputs must be ordered alphabetically
# Inputs: C D
# Outputs: Q
SB_DFF 1 0 2 1
- -
# Inputs: C D E
# Outputs: Q
SB_DFFE 2 0 3 1
- - -
# Inputs: C D R
# Outputs: Q
SB_DFFSR 3 0 3 1
- - -
# Inputs: C D R
# Outputs: Q
SB_DFFR 4 0 3 1
- - -
# Inputs: C D S
# Outputs: Q
SB_DFFSS 5 0 3 1
- - -
# Inputs: C D S
# Outputs: Q
SB_DFFS 6 0 3 1
- - -
# Inputs: C D E R
# Outputs: Q
SB_DFFESR 7 0 4 1
- - - -
# Inputs: C D E R
# Outputs: Q
SB_DFFER 8 0 4 1
- - - -
# Inputs: C D E S
# Outputs: Q
SB_DFFESS 9 0 4 1
- - - -
# Inputs: C D E S
# Outputs: Q
SB_DFFES 10 0 4 1
- - - -
# Inputs: C D
# Outputs: Q
SB_DFFN 11 0 2 1
- -
# Inputs: C D E
# Outputs: Q
SB_DFFNE 12 0 3 1
- - -
# Inputs: C D R
# Outputs: Q
SB_DFFNSR 13 0 3 1
- - -
# Inputs: C D R
# Outputs: Q
SB_DFFNR 14 0 3 1
- - -
# Inputs: C D S
# Outputs: Q
SB_DFFNSS 15 0 3 1
- - -
# Inputs: C D S
# Outputs: Q
SB_DFFNS 16 0 3 1
- - -
# Inputs: C D E R
# Outputs: Q
SB_DFFNESR 17 0 4 1
- - - -
# Inputs: C D E R
# Outputs: Q
SB_DFFNER 18 0 4 1
- - - -
# Inputs: C D E S
# Outputs: Q
SB_DFFNESS 19 0 4 1
- - - -
# Inputs: C D E S
# Outputs: Q
SB_DFFNES 20 0 4 1
- - - -
# (with exceptions for carry in/out)
# Inputs: CI I0 I1
# Outputs: CO
SB_CARRY 21 1 3 1
186 675 609
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
SB_CARRY 1 1 3 1
675 609 186
# Inputs: I0 I1 I2 I3
# Outputs: O
SB_LUT4 22 1 4 1
SB_LUT4 2 1 4 1
661 589 558 465

112
techlibs/ice40/abc_u.box
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@ -1,113 +1,17 @@
# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
# Inputs: C D
# Outputs: Q
SB_DFF 1 0 2 1
- -
# Inputs: C D E
# Outputs: Q
SB_DFFE 2 0 3 1
- - -
# Inputs: C D R
# Outputs: Q
SB_DFFSR 3 0 3 1
- - -
# Inputs: C D R
# Outputs: Q
SB_DFFR 4 0 3 1
- - -
# Inputs: C D S
# Outputs: Q
SB_DFFSS 5 0 3 1
- - -
# Inputs: C D S
# Outputs: Q
SB_DFFS 6 0 3 1
- - -
# Inputs: C D E R
# Outputs: Q
SB_DFFESR 7 0 4 1
- - - -
# Inputs: C D E R
# Outputs: Q
SB_DFFER 8 0 4 1
- - - -
# Inputs: C D E S
# Outputs: Q
SB_DFFESS 9 0 4 1
- - - -
# Inputs: C D E S
# Outputs: Q
SB_DFFES 10 0 4 1
- - - -
# Inputs: C D
# Outputs: Q
SB_DFFN 11 0 2 1
- -
# Inputs: C D E
# Outputs: Q
SB_DFFNE 12 0 3 1
- - -
# Inputs: C D R
# Outputs: Q
SB_DFFNSR 13 0 3 1
- - -
# Inputs: C D R
# Outputs: Q
SB_DFFNR 14 0 3 1
- - -
# Inputs: C D S
# Outputs: Q
SB_DFFNSS 15 0 3 1
- - -
# Inputs: C D S
# Outputs: Q
SB_DFFNS 16 0 3 1
- - -
# Inputs: C D E R
# Outputs: Q
SB_DFFNESR 17 0 4 1
- - - -
# Inputs: C D E R
# Outputs: Q
SB_DFFNER 18 0 4 1
- - - -
# Inputs: C D E S
# Outputs: Q
SB_DFFNESS 19 0 4 1
- - - -
# Inputs: C D E S
# Outputs: Q
SB_DFFNES 20 0 4 1
- - - -
# Inputs: CI I0 I1
# Inputs: I0 I1 CI
# Outputs: CO
SB_CARRY 21 1 3 1
278 675 609
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
SB_CARRY 1 1 3 1
675 609 278
# Inputs: I0 I1 I2 I3
# Outputs: O
SB_LUT4 22 1 4 1
SB_LUT4 2 1 4 1
1285 1231 1205 874

4
techlibs/ice40/cells_sim.v
View File

@ -127,7 +127,7 @@ endmodule
// SiliconBlue Logic Cells
(* abc_box_id = 22, lib_whitebox *)
(* abc_box_id = 2, lib_whitebox *)
module SB_LUT4 (output O, input I0, I1, I2, I3);
parameter [15:0] LUT_INIT = 0;
wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@ -136,7 +136,7 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
assign O = I0 ? s1[1] : s1[0];
endmodule
(* abc_box_id = 21, abc_carry, lib_whitebox *)
(* abc_box_id = 1, abc_carry, lib_whitebox *)
module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule

61
techlibs/xilinx/abc_xc7.box
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@ -1,5 +1,8 @@
# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
# Average across F7[AB]MUX
# Inputs: I0 I1 S0
# Outputs: O
@ -17,51 +20,17 @@ MUXF78 10 1 6 1
190 193 217 223 296 273
# CARRY4 + CARRY4_[ABCD]X
# Inputs: S0 S1 S2 S3 CYINIT DI0 DI1 DI2 DI3 CI
# Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
# Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3
# (NB: carry chain input/output must be last input/output,
# swapped with what normally would have been the last
# output, here: CI <-> S, CO <-> O
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
CARRY4 3 1 10 8
223 - - - 482 - - - - 222
400 205 - - 598 407 - - - 334
523 558 226 - 584 556 537 - - 239
582 618 330 227 642 615 596 438 - 313
340 - - - 536 379 - - - 271
433 469 - - 494 465 445 - - 157
512 548 292 - 592 540 520 356 - 228
508 528 378 380 580 526 507 398 385 114
# SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
# Outputs: DPO SPO
RAM64X1D 4 0 15 2
- - - - - - - 124 124 124 124 124 124 - -
124 124 124 124 124 124 - - - - - - 124 - -
# SLICEM/A6LUT + F7[AB]MUX
# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
# Outputs: DPO SPO
RAM128X1D 5 0 17 2
- - - - - - - - 314 314 314 314 314 314 292 - -
347 347 347 347 347 347 296 - - - - - - - - - -
# Inputs: C CE D R
# Outputs: Q
FDRE 6 0 4 1
- - - -
# Inputs: C CE D S
# Outputs: Q
FDSE 7 0 4 1
- - - -
# Inputs: C CE CLR D
# Outputs: Q
FDCE 8 0 4 1
- - - -
# Inputs: C CE D PRE
# Outputs: Q
FDPE 9 0 4 1
- - - -
482 - - - - 223 - - - 222
598 407 - - - 400 205 - - 334
584 556 537 - - 523 558 226 - 239
642 615 596 438 - 582 618 330 227 313
536 379 - - - 340 - - - 271
494 465 445 - - 433 469 - - 157
592 540 520 356 - 512 548 292 - 228
580 526 507 398 385 508 528 378 380 114

2
techlibs/xilinx/cells_sim.v
View File

@ -289,7 +289,6 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
//(* abc_box_id = 4 /*, lib_whitebox*/ *)
module RAM64X1D (
output DPO, SPO,
input D, WCLK, WE,
@ -307,7 +306,6 @@ module RAM64X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
//(* abc_box_id = 5 /*, lib_whitebox*/ *)
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,