mirror of https://github.com/YosysHQ/yosys.git
Fix for mux_case_* mappings
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@ -157,32 +157,24 @@ module \$shiftx (A, B, Y);
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
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function integer first_B_nonzero;
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integer i;
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begin
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for (i = B_WIDTH-1; i >= 0; i--)
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if (_TECHMAP_CONSTMSK_B_[i] == 1'b0 || _TECHMAP_CONSTVAL_B_ != 1'b0)
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first_B_nonzero = i;
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end
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endfunction
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generate
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genvar i, j;
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if (B_SIGNED) begin
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if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
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// Optimisation to remove B_SIGNED if sign bit of B is constant-0
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
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else
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wire _TECHMAP_FAIL_ = 1;
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end
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else if (Y_WIDTH > 1) begin
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localparam inc = first_B_nonzero();
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for (i = 0; i < Y_WIDTH; i++) begin
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wire [A_WIDTH/Y_WIDTH-1:0] A_i;
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for (j = 0; j*(1<<inc)+i < A_WIDTH; j++)
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assign A_i[j] = A[j*(1<<inc)+i];
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH(B_WIDTH-inc), .Y_WIDTH(1'b1)) bitblast (.A(A_i), .B(B[B_WIDTH-1:inc]), .Y(Y[i]));
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end
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for (i = 0; i < Y_WIDTH; i++)
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A({{i{1'bx}}, A[A_WIDTH-1:i]}), .B(B), .Y(Y[i]));
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end
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else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin
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wire [(A_WIDTH+1)/2-1:0] A_i;
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for (i = 0; i < (A_WIDTH+1)/2; i++)
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assign A_i[i] = A[i*2];
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
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end
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else if (B_WIDTH < 3) begin
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wire _TECHMAP_FAIL_ = 1;
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