riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add +/xilinx/cells_box.v containing models for ABC boxes

This commit is contained in:
Eddie Hung 2019-04-16 11:21:03 -07:00
parent b89bb74452
commit 3ac4977b70
2 changed files with 11 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
techlibs/xilinx/Makefile.inc
View File

@ -31,6 +31,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.box))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_box.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.lut))
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))

10
techlibs/xilinx/cells_box.v Normal file
View File

@ -0,0 +1,10 @@
(* abc_box_id = 1 *)
module MUXF7(output O, input I0, I1, S);
assign O = S ? I1 : I0;
endmodule
(* abc_box_id = 2 *)
module MUXF8(output O, input I0, I1, S);
assign O = S ? I1 : I0;
endmodule