mirror of https://github.com/YosysHQ/yosys.git
Move shregmap until after first techmap
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@ -103,9 +103,9 @@ struct SynthXilinxPass : public Pass
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log(" memory_map\n");
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log(" dffsr2dff\n");
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log(" dff2dffe\n");
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log(" shregmap -init\n");
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log(" opt -full\n");
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log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
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log(" shregmap -init -params -enpol any_or_none\n");
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log(" opt -fast\n");
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log("\n");
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log(" map_luts:\n");
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@ -223,9 +223,9 @@ struct SynthXilinxPass : public Pass
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Pass::call(design, "memory_map");
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Pass::call(design, "dffsr2dff");
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Pass::call(design, "dff2dffe");
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Pass::call(design, "shregmap -init -params -enpol any_or_none");
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Pass::call(design, "opt -full");
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Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
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Pass::call(design, "shregmap -init -params -enpol any_or_none");
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Pass::call(design, "opt -fast");
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}
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