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Add space between -D and _ABC
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@ -203,9 +203,9 @@ struct SynthXilinxPass : public ScriptPass
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{
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if (check_label("begin")) {
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if (vpr)
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run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
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run("read_verilog -lib -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
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else
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run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v");
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run("read_verilog -lib -D _ABC +/xilinx/cells_sim.v");
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run("read_verilog -lib +/xilinx/cells_xtra.v");
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