mirror of https://github.com/YosysHQ/yosys.git
coolrunner2: Combine some for loops together
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@ -38,26 +38,24 @@ struct Coolrunner2SopPass : public Pass {
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log_header(design, "Executing COOLRUNNER2_SOP pass (break $sop cells into ANDTERM/ORTERM cells).\n");
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extra_args(args, 1, design);
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// Find all the $_NOT_ cells
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dict<SigBit, tuple<SigBit, Cell*>> not_cells;
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for (auto module : design->selected_modules())
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{
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pool<Cell*> cells_to_remove;
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SigMap sigmap(module);
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// Find all the $_NOT_ cells
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dict<SigBit, tuple<SigBit, Cell*>> not_cells;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "$_NOT_")
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{
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auto not_input = cell->getPort("\\A")[0];
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auto not_output = cell->getPort("\\Y")[0];
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auto not_input = sigmap(cell->getPort("\\A")[0]);
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auto not_output = sigmap(cell->getPort("\\Y")[0]);
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not_cells[not_input] = tuple<SigBit, Cell*>(not_output, cell);
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}
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}
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}
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pool<tuple<Module*, Cell*>> cells_to_remove;
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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// Process $sop cells
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "$sop")
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@ -79,7 +77,7 @@ struct Coolrunner2SopPass : public Pass {
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sop_output = std::get<0>(not_cell);
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// remove the $_NOT_ cell because it gets folded into the xor
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cells_to_remove.insert(tuple<Module*, Cell*>(module, std::get<1>(not_cell)));
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cells_to_remove.insert(std::get<1>(not_cell));
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}
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// Construct AND cells
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@ -140,15 +138,15 @@ struct Coolrunner2SopPass : public Pass {
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}
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// Finally, remove the $sop cell
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cells_to_remove.insert(tuple<Module*, Cell*>(module, cell));
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cells_to_remove.insert(cell);
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}
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}
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}
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// Actually do the removal now that we aren't iterating
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for (auto mod_and_cell : cells_to_remove)
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{
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std::get<0>(mod_and_cell)->remove(std::get<1>(mod_and_cell));
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// Actually do the removal now that we aren't iterating
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for (auto cell : cells_to_remove)
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{
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module->remove(cell);
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}
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}
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}
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} Coolrunner2SopPass;
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