mirror of https://github.com/YosysHQ/yosys.git
t:$dff* -> t:$dff t:$dffe
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@ -113,7 +113,7 @@ struct SynthXilinxPass : public Pass
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log(" dffsr2dff\n");
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log(" dff2dffe\n");
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log(" opt -full\n");
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log(" simplemap t:$dff* (without -nosrl and without -retime only)\n");
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log(" simplemap t:$dff t:$dffe (without -nosrl and without -retime only)\n");
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log(" shregmap -tech xilinx -minlen 3 (without -nosrl and without -retime only)\n");
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log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
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log(" opt -fast\n");
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@ -266,7 +266,7 @@ struct SynthXilinxPass : public Pass
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Pass::call(design, "opt -full");
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if (!nosrl && !retime) {
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Pass::call(design, "simplemap t:$dff*");
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Pass::call(design, "simplemap t:$dff t:$dffe");
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Pass::call(design, "shregmap -tech xilinx -minlen 3");
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}
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