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Fix synth_ice40 doc regarding -top default

This commit is contained in:
Clifford Wolf 2017-09-29 17:52:57 +02:00
parent dbfd8460a9
commit e64b9d5a4d
1 changed files with 1 additions and 1 deletions
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2
techlibs/ice40/synth_ice40.cc
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@ -38,7 +38,7 @@ struct SynthIce40Pass : public ScriptPass
log("This command runs synthesis for iCE40 FPGAs.\n");
log("\n");
log(" -top <module>\n");
log(" use the specified module as top module (default='top')\n");
log(" use the specified module as top module\n");
log("\n");
log(" -blif <file>\n");
log(" write the design to the specified BLIF file. writing of an output file\n");