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ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set

This commit is contained in:
Eddie Hung 2019-04-19 21:09:55 -07:00
parent 59c993e437
commit af4652522f
2 changed files with 7 additions and 4 deletions
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9
techlibs/ice40/cells_sim.v
View File

@ -127,7 +127,10 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
assign O = I0 ? s1[1] : s1[0];
endmodule
(* abc_box_id = 21, whitebox *)
(* abc_box_id = 21 *)
`ifdef ABC_MODEL
(* whitebox *)
`endif
module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule
@ -135,11 +138,11 @@ endmodule
// Positive Edge SiliconBlue FF Cells
(* abc_box_id = 1, abc_flop *)
`ifdef ABC_FLOPS
`ifdef ABC_MODEL
(* whitebox *)
`endif
module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
`ifndef ABC_FLOPS
`ifndef ABC_MODEL
always @(posedge C)
Q <= D;
`else

2
techlibs/ice40/synth_ice40.cc
View File

@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
{
if (check_label("begin"))
{
run("read_verilog -wb -D ABC_FLOPS +/ice40/cells_sim.v");
run("read_verilog -wb -D ABC_MODEL +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run("proc");
}