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ecp5: Fixing 'X' issues with LUT simulation models 

Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-07-16 15:20:34 +02:00
parent b2c62ff8ef
commit e9ef077266
1 changed files with 19 additions and 6 deletions
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25
techlibs/ecp5/cells_sim.v
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@ -1,8 +1,11 @@
// ---------------------------------------
module LUT4(input A, B, C, D, output Z);
parameter [15:0] INIT = 16'h0000;
assign Z = INIT[{D, C, B, A}];
parameter [15:0] INIT = 16'h0000;
wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];
wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
assign Z = A ? s1[1] : s1[0];
endmodule
// ---------------------------------------
@ -22,8 +25,9 @@ module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
parameter INJECT1_1 = "YES";
// First half
wire LUT4_0 = INIT0[{D0, C0, B0, A0}];
wire LUT2_0 = INIT0[{2'b00, B0, A0}];
wire LUT4_0, LUT2_0;
LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
assign S0 = LUT4_0 ^ gated_cin_0;
@ -32,8 +36,9 @@ module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
// Second half
wire LUT4_1 = INIT1[{D1, C1, B1, A1}];
wire LUT2_1 = INIT1[{2'b00, B1, A1}];
wire LUT4_1, LUT2_1;
LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
assign S1 = LUT4_1 ^ gated_cin_1;
@ -190,6 +195,14 @@ endmodule
// ---------------------------------------
module LUT2(input A, B, output Z);
parameter [3:0] INIT = 4'h0;
wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0];
assign Z = A ? s1[1] : s1[0];
endmodule
// ---------------------------------------
module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
parameter GSR = "ENABLED";
parameter [127:0] CEMUX = "1";