riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)

This commit is contained in:
Eddie Hung 2019-06-03 12:34:55 -07:00
parent d018cd9fe3
commit 0092770317
4 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
techlibs/ice40/abc_hx.box
View File

@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1
# Inputs: I0 I1 I2 I3
# Outputs: O
SB_LUT4 22 0 4 1
SB_LUT4 22 1 4 1
449 400 379 316

4
techlibs/ice40/abc_lp.box
View File

@ -4,7 +4,7 @@
# Inputs: C D
# Outputs: Q
SB_DFF 1 1 2 1
SB_DFF 1 0 2 1
- -
# Inputs: C D E
@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1
# Inputs: I0 I1 I2 I3
# Outputs: O
SB_LUT4 22 0 4 1
SB_LUT4 22 1 4 1
465 558 589 661

4
techlibs/ice40/abc_u.box
View File

@ -4,7 +4,7 @@
# Inputs: C D
# Outputs: Q
SB_DFF 1 1 2 1
SB_DFF 1 0 2 1
- -
# Inputs: C D E
@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1
# Inputs: I0 I1 I2 I3
# Outputs: O
SB_LUT4 22 0 4 1
SB_LUT4 22 1 4 1
1285 1231 1205 874

6
techlibs/ice40/cells_sim.v
View File

@ -127,7 +127,7 @@ endmodule
// SiliconBlue Logic Cells
(* abc_box_id = 22 *)
(* abc_box_id = 22, lib_whitebox *)
module SB_LUT4 (output O, input I0, I1, I2, I3);
parameter [15:0] LUT_INIT = 0;
wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@ -136,8 +136,8 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
assign O = I0 ? s1[1] : s1[0];
endmodule
(* abc_box_id = 21, lib_whitebox *)
module SB_CARRY (output CO, input I0, I1, CI);
(* abc_box_id = 21, abc_carry, lib_whitebox *)
module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule