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xilinx: Still map LUT7/LUT8 to Xilinx specific primitives. 

Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
This commit is contained in:
Tim 'mithro' Ansell 2018-10-08 16:52:12 -07:00
parent 9850de405a
commit b111ea1228
1 changed files with 2 additions and 3 deletions
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5
techlibs/xilinx/synth_xilinx.cc
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@ -235,10 +235,9 @@ struct SynthXilinxPass : public Pass
if (check_label(active, run_from, run_to, "map_cells"))
{
Pass::call(design, "techmap -map +/xilinx/cells_map.v");
if (vpr)
Pass::call(design, "techmap -D NO_LUT -map +/xilinx/cells_map.v");
else
Pass::call(design, "techmap -map +/xilinx/cells_map.v");
Pass::call(design, "techmap -map +/xilinx/lut2lut.v");
Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT");
Pass::call(design, "clean");
}