riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

As per @daveshah1 remove async DFF timing from xilinx

This commit is contained in:
Eddie Hung 2019-06-14 12:43:20 -07:00
parent 7876b5b8be
commit 8fa74287a7
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
techlibs/xilinx/abc_xc7.box
View File

@ -54,9 +54,9 @@ FDSE 7 0 4 1
# Inputs: C CE CLR D
# Outputs: Q
FDCE 8 0 4 1
- - 404 -
- - - -
# Inputs: C CE D PRE
# Outputs: Q
FDPE 9 0 4 1
- - - 404
- - - -