mirror of https://github.com/YosysHQ/yosys.git
Remove SRL16/32 from cells_xtra
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@ -134,8 +134,8 @@ function xtract_cell_decl()
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xtract_cell_decl ROM256X1
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xtract_cell_decl ROM32X1
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xtract_cell_decl ROM64X1
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xtract_cell_decl SRL16E
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xtract_cell_decl SRLC32E
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#xtract_cell_decl SRL16E
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#xtract_cell_decl SRLC32E
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xtract_cell_decl STARTUPE2
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xtract_cell_decl USR_ACCESSE2
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xtract_cell_decl XADC
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@ -3824,22 +3824,6 @@ module ROM64X1 (...);
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input A0, A1, A2, A3, A4, A5;
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endmodule
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module SRL16E (...);
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parameter [15:0] INIT = 16'h0000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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output Q;
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input A0, A1, A2, A3, CE, CLK, D;
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endmodule
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module SRLC32E (...);
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parameter [31:0] INIT = 32'h00000000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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output Q;
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output Q31;
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input [4:0] A;
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input CE, CLK, D;
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endmodule
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module STARTUPE2 (...);
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parameter PROG_USR = "FALSE";
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parameter real SIM_CCLK_FREQ = 0.0;
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