riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed bug causing GP_SPI model to not synthesize

This commit is contained in:
Andrew Zonenberg 2017-08-14 15:32:07 -07:00
parent 68c42f3a19
commit e62362225c
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
techlibs/greenpak4/cells_sim.v
View File

@ -113,8 +113,8 @@ module GP_SPI(
output reg[7:0] RXD_LOW,
output reg INT);
initial DOUT_HIGH = 0;
initial DOUT_LOW = 0;
initial RXD_HIGH = 0;
initial RXD_LOW = 0;
initial INT = 0;
parameter DATA_WIDTH = 8; //byte or word width