mirror of https://github.com/YosysHQ/yosys.git
ice40: Add ice40_braminit pass to allow initialization of BRAM from file
This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will initialize content from a hex file. Same behavior is imlemented in the simulation model and in a new pass for actual synthesis Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut
parent
7a40294e93
commit
e71055cfe8
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@ -1,5 +1,6 @@
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OBJS += techlibs/ice40/synth_ice40.o
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OBJS += techlibs/ice40/ice40_braminit.o
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OBJS += techlibs/ice40/ice40_ffssr.o
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OBJS += techlibs/ice40/ice40_ffinit.o
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OBJS += techlibs/ice40/ice40_opt.o
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@ -326,6 +326,8 @@ module SB_RAM40_4K (
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parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_FILE = "";
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`ifndef BLACKBOX
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wire [15:0] WMASK_I;
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wire [15:0] RMASK_I;
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@ -408,43 +410,46 @@ module SB_RAM40_4K (
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reg [15:0] memory [0:255];
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initial begin
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for (i=0; i<16; i=i+1) begin
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if (INIT_FILE != "")
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$readmemh(INIT_FILE, memory);
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else
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for (i=0; i<16; i=i+1) begin
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`ifdef YOSYS
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memory[ 0*16 + i] <= INIT_0[16*i +: 16];
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memory[ 1*16 + i] <= INIT_1[16*i +: 16];
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memory[ 2*16 + i] <= INIT_2[16*i +: 16];
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memory[ 3*16 + i] <= INIT_3[16*i +: 16];
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memory[ 4*16 + i] <= INIT_4[16*i +: 16];
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memory[ 5*16 + i] <= INIT_5[16*i +: 16];
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memory[ 6*16 + i] <= INIT_6[16*i +: 16];
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memory[ 7*16 + i] <= INIT_7[16*i +: 16];
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memory[ 8*16 + i] <= INIT_8[16*i +: 16];
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memory[ 9*16 + i] <= INIT_9[16*i +: 16];
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memory[10*16 + i] <= INIT_A[16*i +: 16];
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memory[11*16 + i] <= INIT_B[16*i +: 16];
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memory[12*16 + i] <= INIT_C[16*i +: 16];
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memory[13*16 + i] <= INIT_D[16*i +: 16];
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memory[14*16 + i] <= INIT_E[16*i +: 16];
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memory[15*16 + i] <= INIT_F[16*i +: 16];
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memory[ 0*16 + i] <= INIT_0[16*i +: 16];
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memory[ 1*16 + i] <= INIT_1[16*i +: 16];
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memory[ 2*16 + i] <= INIT_2[16*i +: 16];
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memory[ 3*16 + i] <= INIT_3[16*i +: 16];
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memory[ 4*16 + i] <= INIT_4[16*i +: 16];
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memory[ 5*16 + i] <= INIT_5[16*i +: 16];
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memory[ 6*16 + i] <= INIT_6[16*i +: 16];
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memory[ 7*16 + i] <= INIT_7[16*i +: 16];
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memory[ 8*16 + i] <= INIT_8[16*i +: 16];
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memory[ 9*16 + i] <= INIT_9[16*i +: 16];
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memory[10*16 + i] <= INIT_A[16*i +: 16];
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memory[11*16 + i] <= INIT_B[16*i +: 16];
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memory[12*16 + i] <= INIT_C[16*i +: 16];
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memory[13*16 + i] <= INIT_D[16*i +: 16];
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memory[14*16 + i] <= INIT_E[16*i +: 16];
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memory[15*16 + i] <= INIT_F[16*i +: 16];
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`else
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memory[ 0*16 + i] = INIT_0[16*i +: 16];
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memory[ 1*16 + i] = INIT_1[16*i +: 16];
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memory[ 2*16 + i] = INIT_2[16*i +: 16];
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memory[ 3*16 + i] = INIT_3[16*i +: 16];
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memory[ 4*16 + i] = INIT_4[16*i +: 16];
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memory[ 5*16 + i] = INIT_5[16*i +: 16];
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memory[ 6*16 + i] = INIT_6[16*i +: 16];
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memory[ 7*16 + i] = INIT_7[16*i +: 16];
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memory[ 8*16 + i] = INIT_8[16*i +: 16];
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memory[ 9*16 + i] = INIT_9[16*i +: 16];
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memory[10*16 + i] = INIT_A[16*i +: 16];
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memory[11*16 + i] = INIT_B[16*i +: 16];
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memory[12*16 + i] = INIT_C[16*i +: 16];
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memory[13*16 + i] = INIT_D[16*i +: 16];
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memory[14*16 + i] = INIT_E[16*i +: 16];
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memory[15*16 + i] = INIT_F[16*i +: 16];
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memory[ 0*16 + i] = INIT_0[16*i +: 16];
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memory[ 1*16 + i] = INIT_1[16*i +: 16];
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memory[ 2*16 + i] = INIT_2[16*i +: 16];
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memory[ 3*16 + i] = INIT_3[16*i +: 16];
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memory[ 4*16 + i] = INIT_4[16*i +: 16];
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memory[ 5*16 + i] = INIT_5[16*i +: 16];
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memory[ 6*16 + i] = INIT_6[16*i +: 16];
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memory[ 7*16 + i] = INIT_7[16*i +: 16];
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memory[ 8*16 + i] = INIT_8[16*i +: 16];
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memory[ 9*16 + i] = INIT_9[16*i +: 16];
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memory[10*16 + i] = INIT_A[16*i +: 16];
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memory[11*16 + i] = INIT_B[16*i +: 16];
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memory[12*16 + i] = INIT_C[16*i +: 16];
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memory[13*16 + i] = INIT_D[16*i +: 16];
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memory[14*16 + i] = INIT_E[16*i +: 16];
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memory[15*16 + i] = INIT_F[16*i +: 16];
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`endif
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end
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end
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end
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always @(posedge WCLK) begin
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@ -504,6 +509,8 @@ module SB_RAM40_4KNR (
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parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_FILE = "";
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SB_RAM40_4K #(
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.WRITE_MODE(WRITE_MODE),
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.READ_MODE (READ_MODE ),
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@ -522,7 +529,8 @@ module SB_RAM40_4KNR (
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.INIT_C (INIT_C ),
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.INIT_D (INIT_D ),
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.INIT_E (INIT_E ),
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.INIT_F (INIT_F )
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.INIT_F (INIT_F ),
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.INIT_FILE (INIT_FILE )
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) RAM (
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.RDATA(RDATA),
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.RCLK (~RCLKN),
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@ -566,6 +574,8 @@ module SB_RAM40_4KNW (
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parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_FILE = "";
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SB_RAM40_4K #(
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.WRITE_MODE(WRITE_MODE),
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.READ_MODE (READ_MODE ),
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@ -584,7 +594,8 @@ module SB_RAM40_4KNW (
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.INIT_C (INIT_C ),
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.INIT_D (INIT_D ),
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.INIT_E (INIT_E ),
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.INIT_F (INIT_F )
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.INIT_F (INIT_F ),
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.INIT_FILE (INIT_FILE )
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) RAM (
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.RDATA(RDATA),
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.RCLK (RCLK ),
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@ -628,6 +639,8 @@ module SB_RAM40_4KNRNW (
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parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_FILE = "";
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SB_RAM40_4K #(
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.WRITE_MODE(WRITE_MODE),
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.READ_MODE (READ_MODE ),
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@ -646,7 +659,8 @@ module SB_RAM40_4KNRNW (
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.INIT_C (INIT_C ),
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.INIT_D (INIT_D ),
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.INIT_E (INIT_E ),
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.INIT_F (INIT_F )
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.INIT_F (INIT_F ),
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.INIT_FILE (INIT_FILE )
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) RAM (
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.RDATA(RDATA),
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.RCLK (~RCLKN),
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@ -0,0 +1,159 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <bitset>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static void run_ice40_braminit(Module *module)
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{
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for (auto cell : module->selected_cells())
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{
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uint16_t mem[256];
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/* Only consider cells we're interested in */
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if (cell->type != "\\SB_RAM40_4K" &&
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cell->type != "\\SB_RAM40_4KNR" &&
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cell->type != "\\SB_RAM40_4KNW" &&
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cell->type != "\\SB_RAM40_4KNRNW")
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continue;
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if (!cell->hasParam("\\INIT_FILE"))
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continue;
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std::string init_file = cell->getParam("\\INIT_FILE").decode_string();
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cell->unsetParam("\\INIT_FILE");
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if (init_file == "")
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continue;
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/* Open file */
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log("Processing %s : %s\n", RTLIL::id2cstr(cell->name), init_file.c_str());
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std::ifstream f;
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f.open(init_file.c_str());
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if (f.fail()) {
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log("Can not open file `%s`.\n", init_file.c_str());
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continue;
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}
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/* Defaults to 0 */
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memset(mem, 0x00, sizeof(mem));
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/* Process each line */
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bool in_comment = false;
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int cursor = 0;
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while (!f.eof())
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{
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std::string line, token;
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std::getline(f, line);
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for (int i = 0; i < GetSize(line); i++)
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{
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if (in_comment && line.substr(i, 2) == "*/") {
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line[i] = ' ';
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line[i+1] = ' ';
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in_comment = false;
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continue;
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}
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if (!in_comment && line.substr(i, 2) == "/*")
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in_comment = true;
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if (in_comment)
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line[i] = ' ';
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}
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while (1)
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{
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bool set_cursor = false;
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long value;
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token = next_token(line, " \t\r\n");
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if (token.empty() || token.substr(0, 2) == "//")
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break;
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if (token[0] == '@') {
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token = token.substr(1);
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set_cursor = true;
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}
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const char *nptr = token.c_str();
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char *endptr;
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value = strtol(nptr, &endptr, 16);
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if (!*nptr || *endptr) {
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log("Can not parse %s `%s` for %s.\n",
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set_cursor ? "address" : "value",
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nptr, token.c_str()
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);
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continue;
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}
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if (set_cursor)
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cursor = value;
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else if (cursor >= 0 && cursor < 256)
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mem[cursor++] = value;
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else
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log("Attempt to initialize non existent address %d\n", cursor);
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}
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}
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/* Set attributes */
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const char *hex = "0123456789ABCDEF";
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for (int i=0; i<16; i++) {
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std::string val = "";
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for (int j=15; j>=0; j--)
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val += std::bitset<16>(mem[i*16+j]).to_string();
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cell->setParam("\\INIT_" + std::string(1, hex[i]), RTLIL::Const::from_string(val));
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}
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}
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}
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struct Ice40BRAMInitPass : public Pass {
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Ice40BRAMInitPass() : Pass("ice40_braminit", "iCE40: perform SB_RAM40_4K initialization from file") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" ice40_braminit\n");
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log("\n");
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log("This command processes all SB_RAM40_4K blocks with a non-empty INIT_FILE\n");
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log("parameter and converts it inti the required INIT_x attributes\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing ICE40_BRAMINIT pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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// if (args[argidx] == "-???") {
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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run_ice40_braminit(module);
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}
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} Ice40BRAMInitPass;
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PRIVATE_NAMESPACE_END
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