Try -W 300

2019-06-16 12:08:03 -07:00 · 2019-06-16 12:08:03 -07:00 · 1ec450d6bf
parent 5f9ba3ea41
commit 1ec450d6bf
1 changed files with 2 additions and 1 deletions
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@ -25,7 +25,8 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN

-#define XC7_WIRE_DELAY "160"
+#define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate
+                             // to one LUT6 (instead of a LUT5 + LUT2)

 struct SynthXilinxPass : public ScriptPass
 {