mirror of https://github.com/YosysHQ/yosys.git
Merge remote-tracking branch 'origin/xaig' into xc7mux
This commit is contained in:
Eddie Hung
commit
5f9ba3ea41
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@ -59,31 +59,23 @@ void aiger_encode(std::ostream &f, int x)
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struct XAigerWriter
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{
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Module *module;
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bool zinit_mode;
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SigMap sigmap;
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dict<SigBit, bool> init_map;
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pool<SigBit> input_bits, output_bits;
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dict<SigBit, SigBit> not_map, ff_map, alias_map;
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dict<SigBit, SigBit> not_map, alias_map;
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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//pool<SigBit> initstate_bits;
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vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits;
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vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits;
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vector<std::pair<SigBit,SigBit>> ff_bits;
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vector<pair<int, int>> aig_gates;
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vector<int> aig_latchin, aig_latchinit, aig_outputs;
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vector<int> aig_outputs;
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int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
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dict<SigBit, int> aig_map;
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dict<SigBit, int> ordered_outputs;
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dict<SigBit, int> ordered_latches;
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vector<Cell*> box_list;
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//dict<SigBit, int> init_inputs;
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//int initstate_ff = 0;
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int mkgate(int a0, int a1)
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{
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aig_m++, aig_a++;
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@ -97,10 +89,6 @@ struct XAigerWriter
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{
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aig_map[bit] = -1;
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//if (initstate_bits.count(bit)) {
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// log_assert(initstate_ff > 0);
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// aig_map[bit] = initstate_ff;
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//} else
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if (not_map.count(bit)) {
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int a = bit2aig(not_map.at(bit)) ^ 1;
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aig_map[bit] = a;
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@ -123,7 +111,7 @@ struct XAigerWriter
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return aig_map.at(bit);
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}
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XAigerWriter(Module *module, bool zinit_mode, bool holes_mode=false) : module(module), zinit_mode(zinit_mode), sigmap(module)
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XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
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{
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pool<SigBit> undriven_bits;
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pool<SigBit> unused_bits;
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@ -145,14 +133,6 @@ struct XAigerWriter
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for (auto wire : module->wires())
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{
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if (wire->attributes.count("\\init")) {
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SigSpec initsig = sigmap(wire);
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Const initval = wire->attributes.at("\\init");
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for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
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if (initval[i] == State::S0 || initval[i] == State::S1)
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init_map[initsig[i]] = initval[i] == State::S1;
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}
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bool keep = wire->attributes.count("\\keep");
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for (int i = 0; i < GetSize(wire); i++)
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@ -207,16 +187,6 @@ struct XAigerWriter
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continue;
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}
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//if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_"))
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//{
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// SigBit D = sigmap(cell->getPort("\\D").as_bit());
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// SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
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// unused_bits.erase(D);
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// undriven_bits.erase(Q);
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// ff_map[Q] = D;
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// continue;
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//}
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if (cell->type == "$_AND_")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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@ -237,45 +207,8 @@ struct XAigerWriter
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log_assert(!holes_mode);
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//if (cell->type == "$initstate")
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//{
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// SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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// undriven_bits.erase(Y);
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// initstate_bits.insert(Y);
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// continue;
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//}
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RTLIL::Module* inst_module = module->design->module(cell->type);
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//bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false;
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//if (inst_flop) {
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// SigBit d, q;
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// for (const auto &c : cell->connections()) {
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// auto is_input = cell->input(c.first);
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// auto is_output = cell->output(c.first);
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// log_assert(is_input || is_output);
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// RTLIL::Wire* port = inst_module->wire(c.first);
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// for (auto b : c.second.bits()) {
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// if (is_input && port->attributes.count("\\abc_flop_d")) {
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// d = b;
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// SigBit I = sigmap(d);
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// if (I != d)
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// alias_map[I] = d;
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// unused_bits.erase(d);
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// }
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// if (is_output && port->attributes.count("\\abc_flop_q")) {
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// q = b;
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// SigBit O = sigmap(q);
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// if (O != q)
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// alias_map[O] = q;
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// undriven_bits.erase(O);
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// }
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// }
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// }
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// if (!abc_box_seen)
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// abc_box_seen = inst_module->attributes.count("\\abc_box_id");
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// ff_bits.emplace_back(d, q);
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//}
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/*else*/ if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
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if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
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abc_box_seen = true;
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if (!holes_mode) {
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@ -501,7 +434,6 @@ struct XAigerWriter
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log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
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}
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init_map.sort();
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if (holes_mode) {
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struct sort_by_port_id {
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bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
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@ -517,7 +449,6 @@ struct XAigerWriter
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}
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not_map.sort();
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ff_map.sort();
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and_map.sort();
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aig_map[State::S0] = 0;
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@ -529,78 +460,12 @@ struct XAigerWriter
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aig_map[bit] = 2*aig_m;
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}
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for (auto &f : ff_bits) {
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RTLIL::SigBit bit = f.second;
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aig_m++, aig_i++;
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log_assert(!aig_map.count(bit));
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aig_map[bit] = 2*aig_m;
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}
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dict<SigBit, int> ff_aig_map;
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for (auto &c : ci_bits) {
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RTLIL::SigBit bit = std::get<0>(c);
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aig_m++, aig_i++;
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auto r = aig_map.insert(std::make_pair(bit, 2*aig_m));
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if (!r.second)
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ff_aig_map[bit] = 2*aig_m;
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aig_map[bit] = 2*aig_m;
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}
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//if (zinit_mode)
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//{
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// for (auto it : ff_map) {
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// if (init_map.count(it.first))
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// continue;
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// aig_m++, aig_i++;
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// init_inputs[it.first] = 2*aig_m;
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// }
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//}
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for (auto it : ff_map) {
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aig_m++, aig_l++;
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aig_map[it.first] = 2*aig_m;
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ordered_latches[it.first] = aig_l-1;
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if (init_map.count(it.first) == 0)
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aig_latchinit.push_back(2);
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else
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aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
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}
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//if (!initstate_bits.empty() || !init_inputs.empty()) {
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// aig_m++, aig_l++;
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// initstate_ff = 2*aig_m+1;
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// aig_latchinit.push_back(0);
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//}
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//if (zinit_mode)
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//{
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// for (auto it : ff_map)
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// {
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// int l = ordered_latches[it.first];
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// if (aig_latchinit.at(l) == 1)
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// aig_map[it.first] ^= 1;
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// if (aig_latchinit.at(l) == 2)
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// {
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// int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
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// int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
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// aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
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// }
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// }
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//}
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for (auto it : ff_map) {
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int a = bit2aig(it.second);
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int l = ordered_latches[it.first];
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if (zinit_mode && aig_latchinit.at(l) == 1)
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aig_latchin.push_back(a ^ 1);
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else
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aig_latchin.push_back(a);
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}
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//if (!initstate_bits.empty() || !init_inputs.empty())
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// aig_latchin.push_back(1);
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for (auto &c : co_bits) {
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RTLIL::SigBit bit = std::get<0>(c);
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std::get<4>(c) = ordered_outputs[bit] = aig_o++;
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@ -611,13 +476,6 @@ struct XAigerWriter
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ordered_outputs[bit] = aig_o++;
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aig_outputs.push_back(bit2aig(bit));
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}
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for (auto &f : ff_bits) {
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aig_o++;
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RTLIL::SigBit bit = f.second;
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aig_outputs.push_back(ff_aig_map.at(bit));
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}
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}
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void write_aiger(std::ostream &f, bool ascii_mode)
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@ -627,8 +485,6 @@ struct XAigerWriter
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int aig_obcjf = aig_obcj;
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log_assert(aig_m == aig_i + aig_l + aig_a);
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log_assert(aig_l == GetSize(aig_latchin));
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log_assert(aig_l == GetSize(aig_latchinit));
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log_assert(aig_obcjf == GetSize(aig_outputs));
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f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
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@ -639,15 +495,6 @@ struct XAigerWriter
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for (int i = 0; i < aig_i; i++)
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f << stringf("%d\n", 2*i+2);
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for (int i = 0; i < aig_l; i++) {
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if (zinit_mode || aig_latchinit.at(i) == 0)
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f << stringf("%d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i));
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else if (aig_latchinit.at(i) == 1)
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f << stringf("%d %d 1\n", 2*(aig_i+i)+2, aig_latchin.at(i));
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else if (aig_latchinit.at(i) == 2)
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f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2);
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}
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for (int i = 0; i < aig_obc; i++)
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f << stringf("%d\n", aig_outputs.at(i));
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@ -665,15 +512,6 @@ struct XAigerWriter
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}
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else
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{
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for (int i = 0; i < aig_l; i++) {
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if (zinit_mode || aig_latchinit.at(i) == 0)
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f << stringf("%d\n", aig_latchin.at(i));
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else if (aig_latchinit.at(i) == 1)
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f << stringf("%d 1\n", aig_latchin.at(i));
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else if (aig_latchinit.at(i) == 2)
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f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2);
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}
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for (int i = 0; i < aig_obc; i++)
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f << stringf("%d\n", aig_outputs.at(i));
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@ -699,7 +537,7 @@ struct XAigerWriter
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f << "c";
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if (!box_list.empty() || !ff_bits.empty()) {
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if (!box_list.empty()) {
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auto write_buffer = [](std::stringstream &buffer, int i32) {
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int32_t i32_be = to_big_endian(i32);
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buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
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@ -708,14 +546,14 @@ struct XAigerWriter
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std::stringstream h_buffer;
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auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
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write_h_buffer(1);
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log_debug("ciNum = %zu\n", input_bits.size() + ff_bits.size() + ci_bits.size());
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write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
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log_debug("coNum = %zu\n", output_bits.size() + ff_bits.size() + co_bits.size());
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write_h_buffer(output_bits.size() + ff_bits.size()+ co_bits.size());
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log_debug("piNum = %zu\n", input_bits.size() + ff_bits.size());
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write_h_buffer(input_bits.size()+ ff_bits.size());
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log_debug("poNum = %zu\n", output_bits.size() + ff_bits.size());
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write_h_buffer(output_bits.size() + ff_bits.size());
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log_debug("ciNum = %zu\n", input_bits.size() + ci_bits.size());
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write_h_buffer(input_bits.size() + ci_bits.size());
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log_debug("coNum = %zu\n", output_bits.size() + co_bits.size());
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write_h_buffer(output_bits.size() + co_bits.size());
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log_debug("piNum = %zu\n", input_bits.size());
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write_h_buffer(input_bits.size());
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log_debug("poNum = %zu\n", output_bits.size());
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write_h_buffer(output_bits.size());
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log_debug("boxNum = %zu\n", box_list.size());
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write_h_buffer(box_list.size());
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@ -789,21 +627,15 @@ struct XAigerWriter
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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/*if (!ff_bits.empty())*/ {
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std::stringstream r_buffer;
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auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
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log_debug("flopNum = %zu\n", ff_bits.size());
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write_r_buffer(ff_bits.size());
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//int mergeability_class = 1;
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//for (auto cell : ff_bits)
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// write_r_buffer(mergeability_class++);
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std::stringstream r_buffer;
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auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
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write_r_buffer(0);
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f << "r";
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std::string buffer_str = r_buffer.str();
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int32_t buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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}
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f << "r";
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buffer_str = r_buffer.str();
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buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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if (holes_module) {
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// NB: fixup_ports() will sort ports by name
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@ -831,7 +663,7 @@ struct XAigerWriter
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Pass::call(holes_module->design, "clean -purge");
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std::stringstream a_buffer;
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XAigerWriter writer(holes_module, false /*zinit_mode*/, true /* holes_mode */);
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XAigerWriter writer(holes_module, true /* holes_mode */);
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writer.write_aiger(a_buffer, false /*ascii_mode*/);
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holes_module->design->selection_stack.pop_back();
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@ -851,9 +683,7 @@ struct XAigerWriter
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void write_map(std::ostream &f, bool verbose_map)
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{
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dict<int, string> input_lines;
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dict<int, string> init_lines;
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dict<int, string> output_lines;
|
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dict<int, string> latch_lines;
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dict<int, string> wire_lines;
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for (auto wire : module->wires())
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@ -878,22 +708,6 @@ struct XAigerWriter
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continue;
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}
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//if (init_inputs.count(sig[i])) {
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// int a = init_inputs.at(sig[i]);
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// log_assert((a & 1) == 0);
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// init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
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// continue;
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//}
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if (ordered_latches.count(sig[i])) {
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int l = ordered_latches.at(sig[i]);
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if (zinit_mode && (aig_latchinit.at(l) == 1))
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latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
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else
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latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
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continue;
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}
|
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|
||||
if (verbose_map) {
|
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if (aig_map.count(sig[i]) == 0)
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continue;
|
||||
|
|
@ -909,10 +723,6 @@ struct XAigerWriter
|
|||
f << it.second;
|
||||
log_assert(input_lines.size() == input_bits.size());
|
||||
|
||||
init_lines.sort();
|
||||
for (auto &it : init_lines)
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f << it.second;
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|
||||
int box_count = 0;
|
||||
for (auto cell : box_list)
|
||||
f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
|
||||
|
|
@ -922,10 +732,6 @@ struct XAigerWriter
|
|||
f << it.second;
|
||||
log_assert(output_lines.size() == output_bits.size());
|
||||
|
||||
latch_lines.sort();
|
||||
for (auto &it : latch_lines)
|
||||
f << it.second;
|
||||
|
||||
wire_lines.sort();
|
||||
for (auto &it : wire_lines)
|
||||
f << it.second;
|
||||
|
|
@ -946,10 +752,6 @@ struct XAigerBackend : public Backend {
|
|||
log(" -ascii\n");
|
||||
log(" write ASCII version of AIGER format\n");
|
||||
log("\n");
|
||||
log(" -zinit\n");
|
||||
log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
|
||||
log(" uninitialized FFs.\n");
|
||||
log("\n");
|
||||
log(" -map <filename>\n");
|
||||
log(" write an extra file with port and latch symbols\n");
|
||||
log("\n");
|
||||
|
|
@ -960,7 +762,6 @@ struct XAigerBackend : public Backend {
|
|||
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
{
|
||||
bool ascii_mode = false;
|
||||
bool zinit_mode = false;
|
||||
bool verbose_map = false;
|
||||
std::string map_filename;
|
||||
|
||||
|
|
@ -973,10 +774,6 @@ struct XAigerBackend : public Backend {
|
|||
ascii_mode = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-zinit") {
|
||||
zinit_mode = true;
|
||||
continue;
|
||||
}
|
||||
if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
|
||||
map_filename = args[++argidx];
|
||||
continue;
|
||||
|
|
@ -995,7 +792,7 @@ struct XAigerBackend : public Backend {
|
|||
if (top_module == nullptr)
|
||||
log_error("Can't find top module in current design!\n");
|
||||
|
||||
XAigerWriter writer(top_module, zinit_mode);
|
||||
XAigerWriter writer(top_module);
|
||||
writer.write_aiger(*f, ascii_mode);
|
||||
|
||||
if (!map_filename.empty()) {
|
||||
|
|
|
|||
|
|
@ -726,7 +726,7 @@ void AigerReader::parse_aiger_binary()
|
|||
void AigerReader::post_process()
|
||||
{
|
||||
pool<RTLIL::Module*> abc_carry_modules;
|
||||
unsigned ci_count = 0, co_count = 0, flop_count = 0;
|
||||
unsigned ci_count = 0, co_count = 0;
|
||||
for (auto cell : boxes) {
|
||||
RTLIL::Module* box_module = design->module(cell->type);
|
||||
log_assert(box_module);
|
||||
|
|
@ -766,9 +766,6 @@ void AigerReader::post_process()
|
|||
}
|
||||
}
|
||||
|
||||
bool flop = box_module->attributes.count("\\abc_flop");
|
||||
log_assert(!flop || flop_count < flopNum);
|
||||
|
||||
// NB: Assume box_module->ports are sorted alphabetically
|
||||
// (as RTLIL::Module::fixup_ports() would do)
|
||||
for (auto port_name : box_module->ports) {
|
||||
|
|
@ -783,13 +780,6 @@ void AigerReader::post_process()
|
|||
log_assert(wire);
|
||||
log_assert(wire->port_output);
|
||||
wire->port_output = false;
|
||||
|
||||
if (flop && w->attributes.count("\\abc_flop_d")) {
|
||||
RTLIL::Wire* d = outputs[outputs.size() - flopNum + flop_count];
|
||||
log_assert(d);
|
||||
log_assert(d->port_output);
|
||||
d->port_output = false;
|
||||
}
|
||||
}
|
||||
if (w->port_output) {
|
||||
log_assert((piNum + ci_count) < inputs.size());
|
||||
|
|
@ -797,20 +787,11 @@ void AigerReader::post_process()
|
|||
log_assert(wire);
|
||||
log_assert(wire->port_input);
|
||||
wire->port_input = false;
|
||||
|
||||
if (flop && w->attributes.count("\\abc_flop_q")) {
|
||||
wire = inputs[piNum - flopNum + flop_count];
|
||||
log_assert(wire);
|
||||
log_assert(wire->port_input);
|
||||
wire->port_input = false;
|
||||
}
|
||||
}
|
||||
rhs.append(wire);
|
||||
}
|
||||
cell->setPort(port_name, rhs);
|
||||
}
|
||||
|
||||
if (flop) flop_count++;
|
||||
}
|
||||
|
||||
dict<RTLIL::IdString, int> wideports_cache;
|
||||
|
|
|
|||
|
|
@ -65,13 +65,9 @@ bool markgroups;
|
|||
int map_autoidx;
|
||||
SigMap assign_map;
|
||||
RTLIL::Module *module;
|
||||
std::map<RTLIL::SigBit, int> signal_map;
|
||||
std::map<RTLIL::SigBit, RTLIL::State> signal_init;
|
||||
bool recover_init;
|
||||
|
||||
bool clk_polarity, en_polarity;
|
||||
RTLIL::SigSpec clk_sig, en_sig;
|
||||
dict<int, std::string> pi_map, po_map;
|
||||
|
||||
std::string remap_name(RTLIL::IdString abc_name)
|
||||
{
|
||||
|
|
@ -228,13 +224,13 @@ struct abc_output_filter
|
|||
|
||||
void next_line(const std::string &line)
|
||||
{
|
||||
int pi, po;
|
||||
if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
|
||||
log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
|
||||
pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
|
||||
po, po_map.count(po) ? po_map.at(po).c_str() : "???");
|
||||
return;
|
||||
}
|
||||
//int pi, po;
|
||||
//if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
|
||||
// log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
|
||||
// pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
|
||||
// po, po_map.count(po) ? po_map.at(po).c_str() : "???");
|
||||
// return;
|
||||
//}
|
||||
|
||||
for (char ch : line)
|
||||
next_char(ch);
|
||||
|
|
@ -250,11 +246,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
|
|||
module = current_module;
|
||||
map_autoidx = autoidx++;
|
||||
|
||||
signal_map.clear();
|
||||
pi_map.clear();
|
||||
po_map.clear();
|
||||
recover_init = false;
|
||||
|
||||
if (clk_str != "$")
|
||||
{
|
||||
clk_polarity = true;
|
||||
|
|
@ -648,15 +639,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
|
|||
module->connect(conn);
|
||||
}
|
||||
|
||||
if (recover_init)
|
||||
for (auto wire : mapped_mod->wires()) {
|
||||
if (wire->attributes.count("\\init")) {
|
||||
Wire *w = module->wires_[remap_name(wire->name)];
|
||||
log_assert(w->attributes.count("\\init") == 0);
|
||||
w->attributes["\\init"] = wire->attributes.at("\\init");
|
||||
}
|
||||
}
|
||||
|
||||
for (auto &it : cell_stats)
|
||||
log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
|
||||
int in_wires = 0, out_wires = 0;
|
||||
|
|
@ -822,10 +804,6 @@ struct Abc9Pass : public Pass {
|
|||
log_push();
|
||||
|
||||
assign_map.clear();
|
||||
signal_map.clear();
|
||||
signal_init.clear();
|
||||
pi_map.clear();
|
||||
po_map.clear();
|
||||
|
||||
#ifdef ABCEXTERNAL
|
||||
std::string exe_file = ABCEXTERNAL;
|
||||
|
|
@ -976,24 +954,6 @@ struct Abc9Pass : public Pass {
|
|||
}
|
||||
|
||||
assign_map.set(mod);
|
||||
signal_init.clear();
|
||||
|
||||
for (Wire *wire : mod->wires())
|
||||
if (wire->attributes.count("\\init")) {
|
||||
SigSpec initsig = assign_map(wire);
|
||||
Const initval = wire->attributes.at("\\init");
|
||||
for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
|
||||
switch (initval[i]) {
|
||||
case State::S0:
|
||||
signal_init[initsig[i]] = State::S0;
|
||||
break;
|
||||
case State::S1:
|
||||
signal_init[initsig[i]] = State::S0;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!dff_mode || !clk_str.empty()) {
|
||||
abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
|
||||
|
|
@ -1152,10 +1112,6 @@ struct Abc9Pass : public Pass {
|
|||
Pass::call(design, "clean");
|
||||
|
||||
assign_map.clear();
|
||||
signal_map.clear();
|
||||
signal_init.clear();
|
||||
pi_map.clear();
|
||||
po_map.clear();
|
||||
|
||||
log_pop();
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue