Eddie Hung
a2fa1654dc
Merge pull request #1769 from boqwxp/select_cleanup
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Clean up code style and pseudo-private member usage in `passes/cmds/select.cc`
2020-03-17 10:43:45 -07:00
Alberto Gonzalez
9d9bbdce5d
Further clean up `passes/cmds/select.cc`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-16 20:35:19 +00:00
Alberto Gonzalez
70093698f5
Cleanup code style and pseudo-private member usage in `passes/cmds/select.cc`.
2020-03-16 20:35:11 +00:00
Eddie Hung
cdf17c4455
opt_merge: unordered_map -> dict as per @cliffordwolf review
2020-03-16 12:44:33 -07:00
Eddie Hung
9f30d7f843
opt_merge: speedup
2020-03-16 12:43:54 -07:00
Alberto Gonzalez
8ba49a8462
Allow specifying multiple regexes to match in `exec` command output, and also to specify regexes that must _not_ match.
2020-03-16 07:52:57 +00:00
Alberto Gonzalez
e6c09f1e0e
Add `exec` command to run shell commands.
2020-03-16 07:52:57 +00:00
Miodrag Milanovic
8f221118d2
Add YS_ prefix to macros, add explanation and apply to older version as well
2020-03-13 17:19:54 +01:00
Eddie Hung
432a09af80
kernel: SigSpec use more const& + overloads to prevent implicit SigSpec
2020-03-13 08:17:39 -07:00
Miodrag Milanovic
7c54e61979
Use boost xpressive for gcc 4.8
2020-03-13 14:58:35 +01:00
N. Engelhardt
6986371bac
Merge pull request #1751 from boqwxp/add_assert
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Extend `add` command to allow adding $assert cells.
2020-03-12 11:18:35 +01:00
Eddie Hung
dd8ebf7873
Merge pull request #1743 from YosysHQ/eddie/abc9_keep
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abc9: improve (* keep *) handling
2020-03-11 06:32:15 -07:00
Alberto Gonzalez
005dd601ab
Extend `add` command to allow adding cells for verification like $assert, $assume, etc.
2020-03-10 21:49:22 +00:00
David Shah
f2550d45ff
Merge pull request #1753 from YosysHQ/dave/abc9-speedup
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Add ScriptPass::run_nocheck and use for abc9
2020-03-10 13:51:59 +00:00
David Shah
ddcd87b577
Merge pull request #1721 from YosysHQ/dave/tribuf-unused
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deminout: Don't demote inouts with unused bits
2020-03-10 13:51:40 +00:00
Alberto Gonzalez
47537f2e42
Clean up passes/cmds/add.cc code style.
2020-03-10 10:37:10 +00:00
David Shah
b8abf14376
Add ScriptPass::run_nocheck and use for abc9
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Signed-off-by: David Shah <dave@ds0.me>
2020-03-09 14:34:22 +00:00
Eddie Hung
80dcc8a0d1
abc9: for sccs, create a new wire instead of using entirety of existing
2020-03-06 10:30:07 -08:00
Eddie Hung
91a7a74ac4
abc9: (* keep *) wires to be PO only, not PI as well; fix scc handling
2020-03-06 10:20:30 -08:00
Eddie Hung
2335c59e5b
abc: add abc.debug scratchpad option
2020-03-06 10:09:01 -08:00
David Shah
5cae9c6e16
deminout: Don't demote inouts with unused bits
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Signed-off-by: David Shah <dave@ds0.me>
2020-03-04 18:44:38 +00:00
Claire Wolf
879124333f
Merge pull request #1519 from YosysHQ/eddie/submod_po
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submod: several bugfixes
2020-03-03 08:19:06 -08:00
Marcelina Kościelnicka
968956badb
iopadmap: Look harder for already-present buffers. ( #1731 )
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iopadmap: Look harder for already-present buffers.
Fixes #1720 .
2020-03-02 21:40:09 +01:00
Eddie Hung
4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify
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abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
2020-03-02 12:32:27 -08:00
Eddie Hung
de3e5fcdc6
ystests: fix write_smt2_write_smt2_cyclic_dependency_fail
2020-02-28 12:33:55 -08:00
Eddie Hung
78929e8c3d
Fixes for older compilers
2020-02-27 10:17:29 -08:00
Eddie Hung
88d5997c80
abc9_ops: suppress -prep_box warning for abc9_flop
2020-02-27 10:17:29 -08:00
Eddie Hung
6bb3d9f9c0
Make TimingInfo::TimingInfo(SigBit) constructor explicit
2020-02-27 10:17:29 -08:00
Eddie Hung
9dcf204dec
TimingInfo: index by (port_name,offset)
2020-02-27 10:17:29 -08:00
Eddie Hung
7c3b4b80ea
Fix spacing
2020-02-27 10:17:29 -08:00
Eddie Hung
d6cff77751
abc9_ops: still emit delay table even box has no timing
2020-02-27 10:17:29 -08:00
Eddie Hung
683c5ce940
abc9_ops: demote lack of box timing info to warning
2020-02-27 10:17:29 -08:00
Eddie Hung
1ef1ca812b
Get rid of (* abc9_{arrival,required} *) entirely
2020-02-27 10:17:29 -08:00
Eddie Hung
a6fec9fe60
abc9_ops: use TimingInfo for -prep_{lut,box} too
2020-02-27 10:17:29 -08:00
Eddie Hung
3ea5506f81
abc9_ops: use TimingInfo for -prep_{lut,box} too
2020-02-27 10:17:29 -08:00
Eddie Hung
cda4acb544
abc9_ops: add and use new TimingInfo struct
2020-02-27 10:17:29 -08:00
Eddie Hung
e22fee6cdd
abc9_ops: ignore (* abc9_flop *) if not '-dff'
2020-02-27 10:17:29 -08:00
Eddie Hung
7c92b6852f
abc9_ops: sort LUT delays to be ascending
2020-02-27 10:17:29 -08:00
Eddie Hung
7317521c6f
abc9_ops: output LUT area
2020-02-27 10:17:29 -08:00
Eddie Hung
0ed550d83c
abc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto-gen small LUTs
2020-02-27 10:17:29 -08:00
Eddie Hung
12d70ca8fb
xilinx: improve specify functionality
2020-02-27 10:17:29 -08:00
Eddie Hung
577545488a
xilinx: use specify blocks in place of abc9_{arrival,required}
2020-02-27 10:17:29 -08:00
Eddie Hung
0e7c55e2a7
Auto-generate .box/.lut files from specify blocks
2020-02-27 10:17:29 -08:00
Eddie Hung
3d6603792d
abc9_ops: assert on $specify2 properties
2020-02-27 10:17:29 -08:00
Eddie Hung
74f49b1f55
abc9_ops: -prep_box, to be called once
2020-02-27 10:17:29 -08:00
Eddie Hung
5643c1b8c5
abc9_ops: -prep_lut and -write_lut to auto-generate LUT library
2020-02-27 10:17:29 -08:00
Claire Wolf
ab8826ae36
Merge pull request #1709 from rqou/coolrunner2_counter
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Improve CoolRunner-II optimization by using extract_counter pass
2020-02-27 19:05:56 +01:00
Miodrag Milanović
036c46de1e
Merge pull request #1705 from YosysHQ/logger_pass
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Logger pass
2020-02-26 13:32:49 +01:00
Miodrag Milanovic
48eed2860c
Fix line endings
2020-02-23 10:05:21 +01:00
Miodrag Milanovic
010d651450
Update explanation for expect-no-warnings
2020-02-22 10:53:23 +01:00
Miodrag Milanovic
596bb2d443
Check other regex parameters
2020-02-22 10:31:56 +01:00
Alberto Gonzalez
750e7a9a54
Closes #1714 . Fix make failure when NDEBUG=1.
2020-02-22 06:29:11 +00:00
Eddie Hung
760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve
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Improve specify parser
2020-02-21 09:15:17 -08:00
Miodrag Milanovic
419e67c170
check for regex errors
2020-02-20 11:41:37 +01:00
Eddie Hung
1d401a7991
clean: ignore specify-s inside cells when determining whether to keep
2020-02-19 10:45:10 -08:00
Miodrag Milanovic
5641b0248f
Option to expect no warnings
2020-02-17 15:36:06 +01:00
R. Ou
fec7dc5c9e
extract_counter: Implement extracting up counters
2020-02-17 03:08:52 -08:00
R. Ou
940bab6841
extract_counter: Add support for inverted clock enable
2020-02-17 03:08:52 -08:00
R. Ou
5fc180ed2d
extract_counter: Fix clock enable
2020-02-17 03:08:52 -08:00
R. Ou
12fa4a3121
extract_counter: Fix outputting count to module port
2020-02-17 03:08:52 -08:00
R. Ou
508f1ff6a1
extract_counter: Allow forbidding async reset
2020-02-17 03:08:52 -08:00
R. Ou
7b922c0d89
extract_counter: Refactor out extraction settings into struct
2020-02-17 03:08:52 -08:00
Tim 'mithro' Ansell
b9dfdbbfee
show: Add -nobg argument.
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Makes yosys wait for the viewer command to finish before continuing.
2020-02-15 14:03:16 +01:00
Eddie Hung
f9f86fd758
Revert "abc9: fix abc9_arrival for flops"
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This reverts commit f7c0dbecee
.
2020-02-14 16:08:04 -08:00
Miodrag Milanovic
31b7a9c312
Add expect option to logger command
2020-02-14 12:21:16 +01:00
Eddie Hung
0cf7598cd6
Merge pull request #1700 from YosysHQ/eddie/abc9_fixes
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Use (* abc9_init *) attribute, fix use of abc9_arrival for flops
2020-02-13 17:32:54 -08:00
Eddie Hung
3d2a2e8799
iopadmap: fixes as suggested by @mwkmwkmwk
2020-02-13 14:57:06 -08:00
Eddie Hung
f7c0dbecee
abc9: fix abc9_arrival for flops
2020-02-13 12:34:09 -08:00
Eddie Hung
00d41905df
abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr
2020-02-13 12:33:58 -08:00
Eddie Hung
ebb11bcea4
iopadmap: move \init attributes from outpad output to its input
2020-02-13 12:05:14 -08:00
Miodrag Milanovic
0ba2a2b1fa
Add new logger pass
2020-02-13 13:35:29 +01:00
Eddie Hung
c244b27b6d
abc9: cleanup
2020-02-10 10:17:23 -08:00
Eddie Hung
e6bb7b0782
Fix misc.abc9.abc9_abc9_luts
2020-02-07 08:27:45 -08:00
whitequark
60f047f136
memory_bram: add `attr_icase` option.
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Some vendor toolchains use case insensitive matching for values of
attributes that control BRAM inference.
2020-02-06 14:58:20 +00:00
Eddie Hung
505557e93e
Merge pull request #1576 from YosysHQ/eddie/opt_merge_init
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opt_merge: discard \init of '$' cells with 'Q' port when merging
2020-02-05 14:56:26 -08:00
Eddie Hung
0b308c6835
abc9_ops: -reintegrate to use derived_type for box_ports
2020-02-05 14:46:48 -08:00
Eddie Hung
5ebdc0f8e0
Merge pull request #1638 from YosysHQ/eddie/fix1631
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clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
2020-02-05 19:31:18 +01:00
Eddie Hung
0671ae7d79
Merge pull request #1661 from YosysHQ/eddie/abc9_required
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abc9: add support for required times
2020-02-05 18:59:40 +01:00
Marcelina Kościelnicka
34d2fbd2f9
Add opt_lut_ins pass. ( #1673 )
2020-02-03 14:57:17 +01:00
David Shah
4bfd2ef4f3
sv: Improve handling of wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
7e741714df
hierarchy: Correct handling of wildcard port connections with default values
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
5df591c023
hierarchy: Resolve SV wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
1055b6b1dd
Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly
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synth_xilinx: add -dsp-multonly
2020-02-02 14:53:32 +00:00
David Shah
65716c9982
xilinx_dsp: Add multonly scratchpad var to bypass
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-01 15:30:43 +00:00
Eddie Hung
136842b1ef
Merge branch 'master' into eddie/submod_po
2020-02-01 02:14:19 -08:00
Gabriel Somlo
8106c3d31b
abc9: restore ability to use ABCEXTERNAL
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-01-30 15:12:43 -05:00
Claire Wolf
1679682fa3
Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys
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Also some minor fixes to the original PR.
2020-01-29 17:01:24 +01:00
Claire Wolf
4d0118d0c1
Merge pull request #1662 from YosysHQ/dave/opt-reduce-move-check
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opt_reduce: Call check() per run rather than per optimised cell
2020-01-29 15:27:11 +01:00
Eddie Hung
a855f23f22
Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init
2020-01-28 12:46:18 -08:00
Eddie Hung
7939727d14
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts
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Unpermute LUT ordering for ice40/ecp5/xilinx
2020-01-28 11:55:51 -08:00
Claire Wolf
4ddaa70fd6
Merge pull request #1567 from YosysHQ/eddie/sat_init_warning
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sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
2020-01-28 17:40:28 +01:00
N. Engelhardt
086c133ea5
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate
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synth_xilinx: error out if tristate without '-iopad'
2020-01-28 17:24:54 +01:00
David Shah
6fd9cae5ca
opt_reduce: Call check() per run rather than per optimised cell
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Signed-off-by: David Shah <dave@ds0.me>
2020-01-28 09:42:01 +00:00
Pepijn de Vos
409e532433
redirect fuser stderr to /dev/null
2020-01-28 10:02:41 +01:00
Eddie Hung
21ce1b37fb
abc9_ops: -check for negative arrival/required times
2020-01-27 14:22:46 -08:00
Eddie Hung
e18aeda7ed
Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
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Just like Verilog...
2020-01-27 14:02:13 -08:00
Eddie Hung
48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
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Refactor `abc9` pass
2020-01-27 13:29:15 -08:00
Eddie Hung
f2576c096c
Merge branch 'eddie/abc9_refactor' into eddie/abc9_required
2020-01-27 12:29:28 -08:00
Eddie Hung
9009b76a69
abc9_ops: add comments
2020-01-27 11:18:21 -08:00
Eddie Hung
b178761551
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
2020-01-24 11:59:48 -08:00
Eddie Hung
dbf351390e
abc9: -reintegrate recover type from existing cell, check against boxid
2020-01-23 22:45:34 -08:00
Eddie Hung
245873d42d
abc9: warning message if no modules selected
2020-01-23 19:08:51 -08:00
Eddie Hung
f180dba753
abc9_ops: -prep_xaiger to skip (* keep *) cells
2020-01-23 18:56:06 -08:00
Eddie Hung
1d4314d888
abc9_ops -prep_dff: insert async s/r mux in holes when replacing $_DFF_*
2020-01-23 14:58:56 -08:00
Eddie Hung
af0e7637a2
alumacc: undo accidental commit
2020-01-22 20:54:03 -08:00
Eddie Hung
8eb5bb258c
Merge remote-tracking branch 'origin/eddie/abc9_fixes' into eddie/abc9_refactor
2020-01-22 12:30:14 -08:00
Eddie Hung
a94b41011d
abc9: error out if flip-flop init is 1'b1 for '-dff'
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Due to ABC sequential synthesis restriction
2020-01-22 10:08:48 -08:00
Eddie Hung
3b44b53e94
abc9: fix scratchpad entry abc9.verify
2020-01-22 09:36:54 -08:00
Eddie Hung
3d9737c1bd
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-21 16:27:40 -08:00
Claire Wolf
5791c52e1b
Merge pull request #1637 from YosysHQ/mwk/fix-1634
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fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.
2020-01-21 18:37:06 +01:00
Claire Wolf
f165a74824
Merge pull request #1621 from YosysHQ/clifford/fminit
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Add fminit pass
2020-01-20 22:01:57 +01:00
Eddie Hung
6a163b5ddd
xilinx_dsp: another typo; move xilinx specific test
2020-01-17 17:07:03 -08:00
Eddie Hung
db68e4c2a7
ice40_dsp: fix typo
2020-01-17 16:08:04 -08:00
Eddie Hung
e17f3f8c63
Consistency
2020-01-17 16:06:20 -08:00
Eddie Hung
ee500b6d8e
xilinx_dsp: add parameter defaults
2020-01-17 16:05:10 -08:00
Eddie Hung
4985318263
ice40_dsp: add default values for parameters
2020-01-17 15:37:52 -08:00
Eddie Hung
6692e5d558
ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputs
2020-01-17 15:28:02 -08:00
Eddie Hung
d4e188299b
abc9: add some log_{push,pop}() as per @nakengelhardt
2020-01-17 12:00:14 -08:00
Eddie Hung
5a63c19747
abc9_ops: -write_box is empty, output a dummy box to prevent ABC error
2020-01-15 13:14:48 -08:00
Eddie Hung
e30b6bbbf8
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
2020-01-15 09:51:31 -08:00
Eddie Hung
485e08e436
abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *)
2020-01-14 16:33:41 -08:00
Eddie Hung
f60e071e1c
abc9_ops: -check to check abc9_{arrival,required}
2020-01-14 15:24:44 -08:00
Eddie Hung
1c88a6c240
abc9_ops: implement a requireds_cache
2020-01-14 15:20:04 -08:00
Eddie Hung
0e4285ca0d
abc9_ops: generate flop box ids, add abc9_required to FD* cells
2020-01-14 15:05:49 -08:00
Eddie Hung
588a713b54
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-14 14:28:07 -08:00
Eddie Hung
4656f202c6
abc9_ops: -reintegrate to not trim box padding anymore
2020-01-14 14:27:29 -08:00
Eddie Hung
b951ca9e1c
abc9_ops: fix -reintegrate handling of $__ABC9_DELAY
2020-01-14 14:06:02 -08:00
Marcin Kościelnicki
a5d2358a60
fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.
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Fixes #1634 .
2020-01-14 22:49:20 +01:00
Eddie Hung
ec95fbb273
abc9_ops: -prep_times -> -prep_delays; add doc
2020-01-14 13:21:58 -08:00
Eddie Hung
593897ffc0
abc9_ops: cleanup
2020-01-14 13:13:15 -08:00
Eddie Hung
300003cb78
abc9_ops: discard $__ABC9_DELAY boxes
2020-01-14 13:09:54 -08:00
Eddie Hung
915e7dde73
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-14 12:57:56 -08:00
Eddie Hung
654247abe9
abc9_ops/write_xaiger: update doc
2020-01-14 12:40:36 -08:00
Eddie Hung
468386d67d
abc9_ops: -prep_holes -> -prep_xaiger, move padding to write_xaiger
2020-01-14 12:25:45 -08:00
Eddie Hung
53a99ade9c
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-14 11:46:56 -08:00
Eddie Hung
61ffd2d199
Merge pull request #1633 from YosysHQ/eddie/fix_autoname
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autoname: do not rename ports
2020-01-14 11:40:54 -08:00
Eddie Hung
de969adcd8
autoname: do not autoname ports
2020-01-14 10:13:29 -08:00
Eddie Hung
531fddf797
abc9_ops: -break_scc -> -mark_scc using (* keep *), remove -unbreak_scc
2020-01-13 23:42:27 -08:00
Eddie Hung
b678b15c6d
abc9_ops: ignore inouts of all cell outputs for topo ordering
2020-01-13 23:33:37 -08:00
Eddie Hung
2c65e1abac
abc9: break SCC by setting (* keep *) on output wires
2020-01-13 21:45:27 -08:00
Eddie Hung
a2c4d98da7
abc9: add -run option
2020-01-13 19:22:23 -08:00
Eddie Hung
a6d4ea7463
abc9: respect (* keep *) on cells
2020-01-13 19:21:11 -08:00
Eddie Hung
766e16b525
read_aiger: make $and/$not/$lut the prefix not suffix
2020-01-13 17:34:37 -08:00
Eddie Hung
808b388e34
abc9: log which module is being operated on
2020-01-13 09:43:57 -08:00
Eddie Hung
9f3cb981d7
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-13 09:22:42 -08:00
Eddie Hung
f9aae90e7a
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-12 15:19:41 -08:00
Eddie Hung
295e241c07
cleanup
2020-01-11 17:28:24 -08:00
Eddie Hung
79db12f238
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-11 17:26:25 -08:00
Eddie Hung
556ed0e18a
MIssed this merge conflict
2020-01-11 17:05:30 -08:00
Eddie Hung
c063436eea
Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpad
2020-01-11 17:02:20 -08:00
Eddie Hung
11128dccb5
Merge branch 'eddie/abc9_refactor' of github.com:YosysHQ/yosys into eddie/abc9_refactor
2020-01-11 13:56:41 -08:00
Eddie Hung
c820682314
abc9: fix help message, found by @nakengelhardt
2020-01-11 12:11:35 -08:00
Eddie Hung
784fec93c9
abc9: cleanup
2020-01-11 08:42:58 -08:00
Eddie Hung
45d9caf3f9
abc9: remove -nomfs option
2020-01-11 08:08:35 -08:00
Eddie Hung
f24de88f38
log_debug() for abc9_{arrival,required} times
2020-01-10 17:13:27 -08:00
Eddie Hung
ed2aeb498e
Copy-pasta
2020-01-10 15:09:42 -08:00
Eddie Hung
291530c59f
abc9: add abc9.verify and abc9.debug options
2020-01-10 15:04:13 -08:00
Eddie Hung
475d983676
abc9_ops -prep_times: generate flop boxes from abc9_required attr
2020-01-10 14:49:52 -08:00
Eddie Hung
e0af812180
abc9_ops -prep_times: update comment
2020-01-10 12:38:49 -08:00
Eddie Hung
b2259a9201
Add abc9_ops -check, -prep_times, -write_box for required times
2020-01-10 11:45:41 -08:00
Eddie Hung
1f7893bd8c
abc9: fix memory leak
2020-01-10 10:46:06 -08:00
Eddie Hung
d1f8371481
abc9: fix typos
2020-01-10 10:00:09 -08:00
Eddie Hung
e378902f93
Tune abc9.script.flow
2020-01-09 18:16:58 -08:00
Eddie Hung
8b6309747b
Add '-v' to &if for abc9.script.default.fast
2020-01-09 17:49:56 -08:00
Eddie Hung
32946a402d
abc9: start post-fix with semicolon
2020-01-09 17:35:13 -08:00
Eddie Hung
ca70f96503
abc9.script.* constpad entries to start with '+'
2020-01-09 17:17:47 -08:00
Eddie Hung
ef3e84aac9
Revert "abc9: if -script value is a file, then source it, otherwise commands"
...
This reverts commit 0696b7bc9e
.
2020-01-09 17:11:09 -08:00
Eddie Hung
67c9c41f7e
Move abc9.* constpad entries to Abc9Pass::on_register()
2020-01-09 17:10:54 -08:00
Eddie Hung
5e280a3b59
abc9_exe: -box to not require -lut
2020-01-09 14:04:10 -08:00
Clifford Wolf
3fa374a698
Add fminit pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2020-01-09 21:22:54 +01:00
Eddie Hung
4e396ee7a3
abc9_ops: fix reintegration by removing optimised-away boxes
2020-01-09 11:21:03 -08:00
Eddie Hung
589ffead5c
scratchpad entry abc9.if.R to &if -R
2020-01-08 12:13:06 -08:00
Eddie Hung
0696b7bc9e
abc9: if -script value is a file, then source it, otherwise commands
2020-01-08 12:11:55 -08:00
Eddie Hung
050f03f15b
abc9: add time as last script command
2020-01-08 10:55:44 -08:00
Eddie Hung
e230fd8afe
Fix {C} substitution
2020-01-08 10:52:08 -08:00
Eddie Hung
a63e2508fc
Add RTLIL::constpad, init by yosys_setup(); use for abc9
2020-01-08 10:52:08 -08:00
Eddie Hung
88f14b8bca
Cleanup
2020-01-08 10:02:45 -08:00
Eddie Hung
8a47e6ddfd
Fix abc9 help, add labels
2020-01-08 10:00:50 -08:00
Eddie Hung
102f139728
scc to use design->selected_modules() which avoids black/white-boxes
2020-01-07 15:46:36 -08:00
Eddie Hung
dc3b21c1c0
abc9_ops -reintegrate: process box connections
2020-01-07 09:48:57 -08:00
Eddie Hung
6e12ba218b
Fix tabs and cleanup
2020-01-07 09:32:58 -08:00
Eddie Hung
5d9050a955
abc_exe: move 'count_outputs' check to abc
2020-01-07 08:00:32 -08:00
Eddie Hung
cf3a13746d
Add abc9_ops -reintegrate; moved out from now abc9_exe
2020-01-06 15:52:59 -08:00
Eddie Hung
46ed507b93
abc9_map: drop padding in box connections
2020-01-06 15:14:54 -08:00
Eddie Hung
1e2ab19f42
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2020-01-06 15:05:08 -08:00
Eddie Hung
98ee8c14df
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-06 15:02:44 -08:00
Eddie Hung
aa58472a29
Revert "write_xaiger to pad, not abc9_ops -prep_holes"
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This reverts commit b5f60e055d
.
2020-01-06 13:34:45 -08:00
Eddie Hung
2bf442ca01
Cleanup
2020-01-06 13:02:04 -08:00
Eddie Hung
b70e87137d
scc to use design->selected_modules() which avoids black/white-boxes
2020-01-06 12:36:11 -08:00
Eddie Hung
4f13ab823f
Revert "scc command to ignore blackboxes"
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This reverts commit 32695e5032
.
2020-01-06 12:29:13 -08:00
Eddie Hung
36ae2e52e4
Fix bad merge
2020-01-06 12:28:58 -08:00
Eddie Hung
6728a62d92
abc9: uncomment nothing to map message
2020-01-06 12:21:50 -08:00
Eddie Hung
921ff0f5e3
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2020-01-06 12:04:08 -08:00
Eddie Hung
64ace4b0dc
Fixes
2020-01-06 11:53:48 -08:00
Eddie Hung
d152fe961f
Fixes
2020-01-06 11:50:55 -08:00
Eddie Hung
275e937fc1
abc9: remove -markgroups option, since operates on fully selected mod
2020-01-06 10:43:21 -08:00
Eddie Hung
1cf974ff40
abc9: cleanup
2020-01-06 10:26:49 -08:00
N. Engelhardt
fcc1c14adc
error if multiple -g options are given for abc
2020-01-06 19:10:13 +01:00
Eddie Hung
f576721a37
Add abc9.dff scratchpad option
2020-01-06 09:46:02 -08:00
Eddie Hung
45f87bb8ad
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-06 09:44:17 -08:00
N. Engelhardt
7764b62d23
check scratchpad for arguments in abc pass too
2020-01-06 10:46:44 +01:00
N. Engelhardt
b376548fb9
inherit default values when checking scratchpad for arguments
2020-01-06 10:46:10 +01:00
Eddie Hung
b5f60e055d
write_xaiger to pad, not abc9_ops -prep_holes
2020-01-05 10:20:24 -08:00
Eddie Hung
8293a3fe74
Cleanup
2020-01-04 09:30:48 -08:00
Eddie Hung
6556a1347a
Fix when -dff not given
2020-01-04 09:17:01 -08:00
Eddie Hung
930f03e883
Call -prep_holes before aigmap; fix topo ordering
2020-01-03 15:38:18 -08:00
Eddie Hung
a819656972
WIP
2020-01-03 14:59:55 -08:00
Eddie Hung
559f3379e8
Preserve topo ordering from -prep_holes to write_xaiger
2020-01-03 14:37:58 -08:00
Eddie Hung
bb70915fb8
WIP
2020-01-03 13:21:56 -08:00
Eddie Hung
e1f494ab1d
WIP
2020-01-03 13:08:52 -08:00
N. Engelhardt
b2ad781b07
share codepath for scratchpad argument handling with command arguments
2020-01-03 14:11:41 +01:00
N. Engelhardt
341fd872b5
Merge branch 'master' of https://github.com/YosysHQ/yosys into abc_scratchpad_script
2020-01-03 12:28:48 +01:00
Eddie Hung
a050f9c808
Remove a few log_{push,pop}()
2020-01-02 16:14:04 -08:00
Eddie Hung
4eaf415052
aigmap everything
2020-01-02 16:13:44 -08:00
Eddie Hung
32695e5032
scc command to ignore blackboxes
2020-01-02 16:06:39 -08:00
Eddie Hung
7fe268fcdb
Move scc operations out of inner loop
2020-01-02 16:00:26 -08:00
Eddie Hung
222e5e58ad
Cleanup
2020-01-02 15:58:45 -08:00
Eddie Hung
c28bea0382
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2020-01-02 15:57:35 -08:00
Eddie Hung
5f97086302
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-02 15:14:12 -08:00
Eddie Hung
b454735bea
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-02 12:44:06 -08:00
Eddie Hung
ca42af56a4
Update doc
2020-01-02 12:41:57 -08:00
Eddie Hung
8e507bd807
abc9 -keepff -> -dff; refactor dff operations
2020-01-02 12:36:54 -08:00
Eddie Hung
d6242be802
Merge pull request #1601 from YosysHQ/eddie/synth_retime
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"abc -dff" to no longer retime by default
2020-01-02 08:46:24 -08:00
Eddie Hung
6dc63e84ef
Cleanup abc9, update doc for -keepff option
2020-01-01 08:34:57 -08:00
Eddie Hung
c40b1aae42
Restore abc9 -keepff
2020-01-01 08:34:43 -08:00
Eddie Hung
ac808c5e2a
attributes.count() -> get_bool_attribute()
2020-01-01 08:33:32 -08:00
Miodrag Milanovic
e0c879684f
take skip wire bits into account
2020-01-01 16:13:14 +01:00
Eddie Hung
96db05aaef
parse_xaiger to not take box_lookup
2019-12-31 17:06:03 -08:00
Eddie Hung
cac7f5d82e
Do not re-order carry chain ports, just precompute iteration order
2019-12-31 16:12:40 -08:00
Eddie Hung
dacdc6cc94
Remove abc9 -clk option
2019-12-30 22:59:14 -08:00
Eddie Hung
f1bf44ae8f
abc9_ops -prep_dff cope with lack of holes module
2019-12-30 22:58:39 -08:00
Eddie Hung
a367f703ea
Rename struct
2019-12-30 22:56:19 -08:00
Eddie Hung
fad99c2ec7
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2019-12-30 20:14:24 -08:00
Eddie Hung
b42b64e8ed
Move Pass::call() out of abc9_ops into abc9
2019-12-30 19:23:54 -08:00
Eddie Hung
52f649dcfd
Use function arg
2019-12-30 18:47:06 -08:00
Eddie Hung
0317a2b476
holes_module to be whitebox
2019-12-30 18:46:22 -08:00
Eddie Hung
b50de28c04
Add abc9_ops -prep_holes
2019-12-30 18:00:49 -08:00
Eddie Hung
16c4ec7eda
Add abc9_ops -prep_dff
2019-12-30 16:36:33 -08:00
Eddie Hung
88b9c8d46d
Restore count_outputs, move process check to abc
2019-12-30 16:29:08 -08:00
Eddie Hung
dbffbeef5c
Fix struct name
2019-12-30 16:21:20 -08:00
Eddie Hung
7649ec72c9
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2019-12-30 16:20:58 -08:00
Eddie Hung
4c3f517425
Remove delay targets doc
2019-12-30 16:11:42 -08:00
Eddie Hung
658f424d7d
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2019-12-30 16:01:38 -08:00
Eddie Hung
0735572934
write_xaiger to use scratchpad for stats; cleanup abc9
2019-12-30 15:35:33 -08:00
Eddie Hung
22fe931c86
Grammar
2019-12-30 15:07:15 -08:00
Eddie Hung
fc4b8b8991
Remove submod changes
2019-12-30 14:56:14 -08:00
Eddie Hung
405e974fe5
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-30 14:31:42 -08:00
Eddie Hung
d7ada66497
Add "synth_xilinx -dff" option, cleanup abc9
2019-12-30 14:13:16 -08:00
Eddie Hung
566d9fb77f
Revert "ABC to call retime all the time"
...
This reverts commit 9aa94370a5
.
2019-12-30 13:28:29 -08:00
Eddie Hung
52a27700e2
Grammar
2019-12-30 12:26:39 -08:00
Eddie Hung
f348ffa44d
abc9_techmap -> _map; called from abc9 script pass along with abc9_ops
2019-12-28 05:07:46 -08:00
Eddie Hung
ec25394808
Rename abc9.cc -> abc9_techmap.cc
2019-12-28 03:16:28 -08:00
Miodrag Milanovic
3e14ff1667
fixed invalid char
2019-12-25 20:38:48 +01:00
Marcin Kościelnicki
a24596def3
iopadmap: Emit tristate buffers with const OE for some edge cases.
2019-12-25 17:37:58 +01:00
Marcin Kościelnicki
e226a8f7f1
Minor nit fixes
2019-12-25 15:39:40 +01:00
Eddie Hung
1d0ac659ad
Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too
2019-12-23 14:40:59 -08:00
Eddie Hung
75acaff6f5
Fix CEA/CEB check
2019-12-23 14:22:13 -08:00
Eddie Hung
edabe73377
Fix checking CE[AB] and for direct connections
2019-12-23 13:41:26 -08:00
Eddie Hung
71cac30309
Support unregistered cascades for A and B inputs
2019-12-23 12:38:18 -08:00
Eddie Hung
d00533eaa8
Add DSP48A* PCOUT -> PCIN cascade support
2019-12-23 11:42:46 -08:00
Eddie Hung
509070f82f
Disable clock domain partitioning in Yosys pass, let ABC do it
2019-12-23 08:36:20 -08:00
Marcin Kościelnicki
666c6128a9
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
Eddie Hung
1ea1e8e54f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 13:56:13 -08:00
Eddie Hung
1482f32d53
Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut
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Interpret "abc9 -lut" as lut string only if [0-9:]
2019-12-20 13:09:00 -08:00
Eddie Hung
f5e0a07ad6
Add $_FF_ and $_SR* courtesy of @mwkmwkmwk
2019-12-20 13:00:04 -08:00
Eddie Hung
d038cea3c7
More stringent check for flop cells
2019-12-20 12:32:00 -08:00
Eddie Hung
979bf36fb0
Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t
2019-12-19 11:23:41 -08:00
Eddie Hung
94f15f023c
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-19 10:29:40 -08:00
Eddie Hung
269ba56a6d
Merge pull request #1581 from YosysHQ/clifford/fix1565
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Fix sim for assignments with lhs<rhs size
2019-12-19 12:24:27 -05:00
Eddie Hung
3b559de6e9
Interpret "abc9 -lut" as lut string only if [0-9:]
2019-12-18 12:21:12 -08:00
Eddie Hung
d0afe4e10d
Merge branch 'master' of github.com:YosysHQ/yosys
2019-12-18 12:08:38 -08:00
Eddie Hung
b2a42e1fac
Merge pull request #1572 from nakengelhardt/scratchpad_pass
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add a command to read/modify scratchpad contents
2019-12-18 13:55:44 -05:00
Marcin Kościelnicki
a235250403
xilinx: Add xilinx_dffopt pass ( #1557 )
2019-12-18 13:43:43 +01:00
N. Engelhardt
3671ecc7d0
use extra_args
2019-12-18 12:30:30 +01:00
Eddie Hung
c9c77a90b3
Remove &verify -s
2019-12-17 16:11:54 -08:00
Eddie Hung
b1b99e421e
Use pool<> instead of std::set<> to preserver ordering
2019-12-17 16:10:40 -08:00
N. Engelhardt
c8bc1793a4
check scratchpad variable abc9.scriptfile
2019-12-17 19:39:55 +01:00
Clifford Wolf
41ed6ca7a5
Fix sim for assignments with lhs<rhs size, fixes #1565
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-12-17 17:36:30 +01:00
Eddie Hung
dccd7eb39f
Cleanup
2019-12-17 00:25:08 -08:00
Eddie Hung
33e6d05585
Enforce non-existence
2019-12-16 17:06:30 -08:00
Eddie Hung
d9bf7061cd
Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop
2019-12-16 16:49:48 -08:00
Eddie Hung
187e1c46e6
Update doc
2019-12-16 14:48:53 -08:00
Eddie Hung
4158ce4eda
More sloppiness, thanks @dh73 for spotting
2019-12-16 13:56:45 -08:00
Eddie Hung
6b384861e4
Oops
2019-12-16 13:31:05 -08:00
Eddie Hung
503d1db551
Implement 'attributes' grammar
2019-12-16 12:58:13 -08:00
Eddie Hung
952d62991f
Merge branch 'diego/memattr' of https://github.com/dh73/yosys into diego/memattr
2019-12-16 12:07:49 -08:00
Diego H
87e21b0122
Fixing compiler warning/issues. Moving test script to the correct place
2019-12-16 10:23:45 -06:00
N. Engelhardt
abcd82daca
add assert option to scratchpad command
2019-12-16 14:00:21 +01:00
Diego H
b35559fc33
Merging attribute rules into a single match block; Adding tests
2019-12-15 23:33:09 -06:00
Alyssa Milburn
e709fd3da1
Fix opt_expr.eqneq.cmpzero debug print
2019-12-15 20:40:38 +01:00
Diego H
266993408a
Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific
2019-12-13 15:43:24 -06:00
Eddie Hung
83d36394f8
opt_merge to discard \init of '$' cells with 'Q' port when merging
2019-12-13 10:26:37 -08:00
N. Engelhardt
91f427d719
check scratchpad variables for custom abc scripts
2019-12-13 12:54:52 +01:00
N. Engelhardt
ce3615b367
add periods and newlines to help message
2019-12-13 10:28:34 +01:00
Eddie Hung
bea15b537b
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-12 14:57:17 -08:00
Eddie Hung
abf99d4dae
tribuf: set scratchpad boolean 'tribuf.added_something'
2019-12-12 14:32:29 -08:00
N. Engelhardt
1187e91c2f
add test and make help message more verbose
2019-12-12 20:51:59 +01:00
N. Engelhardt
4c7cda1c8b
add a command to read/modify scratchpad contents
2019-12-12 16:25:03 +01:00
Eddie Hung
9a892199f7
Suppress warning message for init[i] = 1'bx
2019-12-11 11:27:10 -08:00
Eddie Hung
7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
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Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
2019-12-09 17:38:48 -08:00
Eddie Hung
36a88be609
ice40_wrapcarry -unwrap to preserve 'src' attribute
2019-12-09 14:28:54 -08:00
Eddie Hung
bbdf2452b3
-unwrap to create $lut not SB_LUT4 for opt_lut
2019-12-09 13:27:09 -08:00
Eddie Hung
500ed9b501
Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4
2019-12-09 12:45:22 -08:00
Eddie Hung
e05372778a
ice40_wrapcarry to really preserve attributes via -unwrap option
2019-12-09 11:48:28 -08:00
Eddie Hung
a46a7e8a67
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-06 23:22:52 -08:00
Eddie Hung
946d5854c0
Drop keep=0 attributes on SB_CARRY
2019-12-06 17:27:47 -08:00
Eddie Hung
ab667d3d47
Call abc9 with "&write -n", and parse_xaiger() to cope
2019-12-06 16:35:57 -08:00
Eddie Hung
fce527f4f7
Fix abc9 re-integration, remove abc9_control_wire, use cell->type as
...
as part of clock domain for mergeability class
2019-12-06 16:20:18 -08:00
Eddie Hung
01a3cc29ba
abc9 to do clock partitioning again
2019-12-05 17:26:22 -08:00
Eddie Hung
02786b0aa0
Remove clkpart
2019-12-05 17:25:26 -08:00
Eddie Hung
a7e0cca480
Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER
2019-12-05 07:01:18 -08:00
Marcin Kościelnicki
2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. ( #1527 )
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The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
2019-12-04 08:44:08 +01:00
Eddie Hung
d66d06b91d
Add assertion
2019-12-03 19:21:42 -08:00
Eddie Hung
a181ff66d3
Add abc9_init wire, attach to abc9_flop cell
2019-12-03 18:47:09 -08:00
Eddie Hung
5897b918b3
ice40_wrapcarry to preserve SB_CARRY's attributes
2019-12-03 14:48:11 -08:00
Eddie Hung
a265a84632
Use pool instead of std::set for determinism
2019-12-02 01:28:28 -08:00
Eddie Hung
6398b7c17c
Cleanup
2019-12-01 23:43:28 -08:00
Eddie Hung
1d87488795
Use pool instead of std::set for determinism
2019-12-01 23:26:17 -08:00
Eddie Hung
4ac1b92df3
Use pool<> not std::set<> for determinism
2019-12-01 23:19:32 -08:00
David Shah
e9ce4e658b
abc9: Fix breaking of SCCs
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Signed-off-by: David Shah <dave@ds0.me>
2019-12-01 20:44:56 +00:00
Eddie Hung
a26c52394f
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-28 12:58:30 -08:00
Eddie Hung
b3a66dff7c
Move \init signal for non-port signals as long as internally driven
2019-11-28 12:57:36 -08:00
Eddie Hung
130d3b9639
Fix multiple driver issue
2019-11-27 13:23:31 -08:00
Eddie Hung
ac5b5e97bc
Fix multiple driver issue
2019-11-27 13:21:59 -08:00
Eddie Hung
4bac6b13be
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-27 10:17:10 -08:00
Eddie Hung
cd2af66099
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-27 08:19:13 -08:00
Eddie Hung
1c0ee4f786
Do not replace constants with same wire
2019-11-27 08:18:41 -08:00
Eddie Hung
6464dc35ec
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
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xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
2019-11-27 08:00:22 -08:00
Clifford Wolf
41e0ddf4f4
Merge pull request #1501 from YosysHQ/dave/mem_copy_attr
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memory_collect: Copy attr from RTLIL::Memory to cell
2019-11-27 11:25:23 +01:00
Eddie Hung
6338615aa1
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-27 01:02:16 -08:00
Eddie Hung
c7aa2c6b79
Cleanup
2019-11-27 01:01:24 -08:00
Eddie Hung
cb05fe0f70
Check for nullptr
2019-11-27 00:51:39 -08:00
Eddie Hung
d960feeeb0
Stray log_dump
2019-11-27 00:50:25 -08:00
Eddie Hung
8c813632b6
Revert "submod to bitty rather bussy, for bussy wires used as input and output"
...
This reverts commit cba3073026
.
2019-11-27 00:48:22 -08:00
Eddie Hung
969f511415
Promote output wires in sigmap so that can be detected
2019-11-26 23:39:14 -08:00
Eddie Hung
5e487b103c
Fix submod -hidden
2019-11-26 23:26:25 -08:00
Eddie Hung
435d33c373
Add -hidden option to submod
2019-11-26 23:26:12 -08:00
Marcin Kościelnicki
fdcbda195b
opt_share: Fix handling of fine cells.
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Fixes #1525 .
2019-11-27 08:01:07 +01:00
Eddie Hung
2105ae176a
Check for either sign or zero extension for postAdd packing
2019-11-26 22:51:00 -08:00
Eddie Hung
09637dd3e4
Fix submod -hidden
2019-11-26 11:57:26 -08:00
Eddie Hung
3027f015c2
clkpart to use 'submod -hidden'
2019-11-26 11:35:32 -08:00
Eddie Hung
e8aa92ca35
Add -hidden option to submod
2019-11-26 11:35:15 -08:00
Eddie Hung
eb666b4677
Update docs with bullet points
2019-11-26 11:12:58 -08:00
Eddie Hung
0d7ba77426
Move \init from source wire to submod if output port
2019-11-25 16:07:47 -08:00
Eddie Hung
6831510f5b
Fix debug
2019-11-25 12:59:34 -08:00
Eddie Hung
d087024caf
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-25 12:42:09 -08:00
Eddie Hung
180cb39395
abc9 to contain time call
2019-11-25 12:35:57 -08:00
Eddie Hung
f50b6422b0
abc9 to no longer to clock partitioning, operate on whole modules only
2019-11-25 12:35:38 -08:00
Eddie Hung
63b7a48fbc
clkpart to analyse async flops too
2019-11-25 12:04:11 -08:00
Marcin Kościelnicki
6cdea425b8
clkbufmap: Add support for inverters in clock path.
2019-11-25 20:40:39 +01:00
Eddie Hung
23ecf12bbf
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-23 10:29:03 -08:00
Eddie Hung
15aa3f460d
More oopsies
2019-11-23 10:28:46 -08:00
Eddie Hung
bf1167bc64
Conditioning abc9 on POs not accurate due to cells
2019-11-23 10:26:55 -08:00
Eddie Hung
7b2bccb3d3
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-23 10:18:06 -08:00
Eddie Hung
722eeacc09
Print ".en=" only if there is an enable signal
2019-11-23 10:17:31 -08:00
Eddie Hung
907c8aeaef
Escape IdStrings
2019-11-23 10:16:56 -08:00
Eddie Hung
165f5cb6cf
More sane naming of submod
2019-11-23 10:01:09 -08:00
Eddie Hung
66ff0511a0
Add -set_attr option, -unpart to take attr name
2019-11-23 09:52:17 -08:00
Eddie Hung
fb49da21bd
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-23 08:39:19 -08:00
Eddie Hung
96941aacbb
Do not use log_signal() for empty SigSpec to prevent "{ }"
2019-11-22 23:29:10 -08:00
Eddie Hung
736b96b186
Call submod once, more meaningful submod names, ignore largest domain
2019-11-22 23:16:15 -08:00
Eddie Hung
1851f4b488
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-22 23:01:18 -08:00
Eddie Hung
d223e11a72
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 22:28:35 -08:00
Eddie Hung
cba3073026
submod to bitty rather bussy, for bussy wires used as input and output
2019-11-22 20:53:58 -08:00
Eddie Hung
900c806d4e
Move clkpart into passes/hierarchy
2019-11-22 17:25:53 -08:00
Eddie Hung
2c5dfd802d
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 17:24:45 -08:00
Eddie Hung
8119383f81
Constant driven signals are also an input to submodules
2019-11-22 17:23:51 -08:00
Eddie Hung
89a4a4d90f
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 17:04:33 -08:00
Eddie Hung
573396851a
Oops
2019-11-22 17:03:30 -08:00
Eddie Hung
bf7d36627e
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-22 17:00:35 -08:00
Eddie Hung
95af8f56e4
Only action if there is more than one clock domain
2019-11-22 17:00:11 -08:00
Eddie Hung
00d76f6cc4
Replace TODO
2019-11-22 16:58:08 -08:00
Eddie Hung
0806b8e398
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 16:50:56 -08:00
Eddie Hung
6a52897aee
sigmap(wire) should inherit port_output status of POs
2019-11-22 16:48:11 -08:00
Eddie Hung
698854955c
Merge branch 'eddie/clkpart' into xaig_dff
2019-11-22 15:41:48 -08:00
Eddie Hung
84153288bb
Brackets
2019-11-22 15:41:34 -08:00
Eddie Hung
3df191cec5
Entry in Makefile.inc
2019-11-22 15:41:23 -08:00
Eddie Hung
bd56161775
Merge branch 'eddie/clkpart' into xaig_dff
2019-11-22 15:38:48 -08:00
Eddie Hung
856a3dc98d
New 'clkpart' to {,un}partition design according to clock/enable
2019-11-22 15:35:51 -08:00
Clifford Wolf
03fb92ed6f
Add "opt_mem" pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-22 17:45:22 +01:00
Eddie Hung
c4ec42ac38
When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_
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Since they should be captured downwards from the owning flop
2019-11-21 16:17:03 -08:00
David Shah
ca99b1ee8d
proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-21 20:46:41 +00:00
Eddie Hung
729c6b93e8
endomain -> ctrldomain
2019-11-20 14:32:01 -08:00
Eddie Hung
09ee96e8c2
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-19 15:40:39 -08:00
Marcin Kościelnicki
15232a48af
Fix #1462 , #1480 .
2019-11-19 08:57:39 +01:00
David Shah
7ff5d6d30a
memory_collect: Copy attr from RTLIL::Memory to cell
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-18 13:58:03 +00:00
Marcin Kościelnicki
38e72d6e13
Fix #1496 .
2019-11-18 04:16:48 +01:00
Clifford Wolf
527434de49
Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arst
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wreduce: Don't trim zeros or sext when not matching ARST_VALUE
2019-11-17 10:42:30 +01:00
David Shah
f5804a84fd
wreduce: Don't trim zeros or sext when not matching ARST_VALUE
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-14 18:43:15 +00:00
Clifford Wolf
e907ee4fde
Merge pull request #1490 from YosysHQ/clifford/autoname
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Add "autoname" pass and use it in "synth_ice40"
2019-11-14 18:03:44 +01:00
Clifford Wolf
07c854b7af
Add "autoname" pass and use it in "synth_ice40"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-13 13:41:16 +01:00
whitequark
ab0fb19cff
Merge pull request #1488 from whitequark/flowmap-fixes
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flowmap: fix a few crashes
2019-11-13 11:57:17 +00:00
Clifford Wolf
4be5a0fd7c
Update fsm_detect bugfix
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-12 17:31:30 +01:00
Clifford Wolf
16df8f5a32
Bugfix in fsm_detect
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-12 14:26:02 +01:00
whitequark
c68722818a
flowmap: when doing mincut, ensure source is always in X, not X̅.
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Fixes #1475 .
2019-11-12 00:15:43 +00:00
whitequark
eef32195bd
flowmap: don't break if that creates a k+2 (and larger) LUT either.
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Fixes #1405 .
2019-11-11 23:13:00 +00:00
Sean Cross
82f60ba938
Makefile: don't assume python is called `python3`
...
On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`. The build system assumes
that python is called `python3`, which breaks under this architecture.
There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS. Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.
Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-10-19 14:04:52 +08:00
Clifford Wolf
b8774ae849
Fix dffmux peepopt init handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 11:40:32 +02:00
Clifford Wolf
bb0851bfc5
Move GENERATE_PATTERN macro to separate utility header
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 11:40:01 +02:00
Clifford Wolf
af61d92441
Disable left-over log_debug in peepopt_dffmux.pmg
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 10:43:47 +02:00
Eddie Hung
304e5f9ea4
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-08 13:03:06 -07:00
Eddie Hung
ea54b5ea61
Revert "Be mindful that sigmap(wire) could have dupes when checking \init"
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This reverts commit f46ac1df9f
.
2019-10-08 12:41:24 -07:00
Eddie Hung
cfc181cba9
Merge pull request #1432 from YosysHQ/eddie/fix1427
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Refactor peepopt_dffmux and be sensitive to \init when trimming
2019-10-08 12:38:29 -07:00
Eddie Hung
4c89a4e642
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync
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async2sync to be called by equiv_opt only when -async2sync given
2019-10-08 10:53:44 -07:00
Eddie Hung
9fd2ddb14c
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
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Rename abc_* names/attributes to more precisely be abc9_*
2019-10-08 10:53:38 -07:00
Eddie Hung
472b5d33a6
Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_comments
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Add notes and comments for xilinx_dsp
2019-10-08 10:53:30 -07:00
Eddie Hung
2cb2116b4c
Use "abc9_period" attribute for delay target
2019-10-07 15:03:44 -07:00
Clifford Wolf
4072a96663
Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarry
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Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
2019-10-06 12:11:20 +02:00
Eddie Hung
3879ca1398
Do not require changes to cells_sim.v; try and work out comb model
2019-10-05 22:55:18 -07:00
Eddie Hung
5c68da4150
Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
2019-10-05 09:27:12 -07:00
Clifford Wolf
10d0bad67e
Update README.md
2019-10-05 18:13:04 +02:00
Eddie Hung
f90a4b1e24
Missed this
2019-10-05 08:57:37 -07:00
Eddie Hung
991c2ca95b
Add comment on why we have to match for clock-enable/reset muxes
2019-10-05 08:56:37 -07:00
Eddie Hung
ebb059896a
Add note on pattern detector
2019-10-05 08:53:01 -07:00
Miodrag Milanović
7c074ef844
Merge pull request #1436 from YosysHQ/mmicko/msvc_fix
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Fixes for MSVC build
2019-10-05 07:48:30 +02:00
Eddie Hung
792cd31052
Add comments for xilinx_dsp_cascade
2019-10-04 22:31:04 -07:00
Eddie Hung
12fd2ec4f0
Improve comments for xilinx_dsp_CREG
2019-10-04 22:31:04 -07:00
Eddie Hung
14e4aeece6
Fix comment
2019-10-04 22:31:04 -07:00
Eddie Hung
8027ebf05b
Restore optimisation for sigM.empty()
2019-10-04 22:31:04 -07:00
Eddie Hung
77d7a5c14a
Retry on fixing TODOs
2019-10-04 22:31:04 -07:00
Eddie Hung
52583ecff8
Revert "Fix TODOs"
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This reverts commit 8674a6c68d563908014d16671567459499c6dc99.
2019-10-04 22:31:04 -07:00
Eddie Hung
6d68972619
More comments, cleanup
2019-10-04 22:31:04 -07:00
Eddie Hung
7de9c33931
Fix TODOs
2019-10-04 22:31:04 -07:00
Eddie Hung
983068103e
Consistency
2019-10-04 22:31:04 -07:00
Eddie Hung
cf82b38478
Add comments for xilinx_dsp
2019-10-04 22:31:04 -07:00
Eddie Hung
a5ac33f230
Merge branch 'master' into eddie/abc_to_abc9
2019-10-04 17:53:20 -07:00
Eddie Hung
f0cadb0de8
Fix from merge
2019-10-04 17:52:19 -07:00
Eddie Hung
bbc0e06af3
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-04 17:39:08 -07:00
Eddie Hung
0acc51c3d8
Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`
2019-10-04 17:35:43 -07:00
Eddie Hung
7959e9d6b2
Fix merge issues
2019-10-04 17:21:14 -07:00
Eddie Hung
7a45cd5856
Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
2019-10-04 16:58:55 -07:00
Eddie Hung
74ef8feeaf
Fix xilinx_dsp for unsigned extensions
2019-10-04 16:46:15 -07:00
Eddie Hung
aae2b9fd9c
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
Eddie Hung
84f978bdc2
Add -async2sync to help text as per @daveshah1
2019-10-04 10:17:46 -07:00
Miodrag Milanovic
c0b14cfea7
Fixes for MSVC build
2019-10-04 16:29:46 +02:00
Eddie Hung
549d6ea467
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-03 10:55:23 -07:00
Eddie Hung
a9efd2e81c
Restore part of doc
2019-10-03 10:51:53 -07:00
Eddie Hung
7a6dec1cef
Add new -async2sync option
2019-10-03 10:30:51 -07:00
Eddie Hung
8765ec3c27
Revert "equiv_opt to call async2sync when not -multiclock like SymbiYosys"
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This reverts commit a39505e329
.
2019-10-03 10:07:15 -07:00
Eddie Hung
c6d15c9aad
Revert "Update doc for equiv_opt"
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This reverts commit a274b7cc86
.
2019-10-03 10:07:03 -07:00
Clifford Wolf
0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select
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Add -select option to aigmap
2019-10-03 11:54:04 +02:00
Clifford Wolf
afdc990595
Merge pull request #1429 from YosysHQ/clifford/checkmapped
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Add "check -mapped"
2019-10-03 11:50:53 +02:00
Clifford Wolf
3e27b2846b
Add "check -allow-tbuf"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-03 11:49:56 +02:00
Eddie Hung
e9645c7fa7
Fix broken CI, check reset even for constants, trim rstmux
2019-10-02 21:26:26 -07:00
Eddie Hung
c6a55d948a
Merge branch 'eddie/fix_sat_init' into eddie/fix1427
2019-10-02 18:07:38 -07:00
Eddie Hung
d99810ad8a
Refactor peepopt_dffmux and be sensitive to \init when trimming
2019-10-02 18:01:45 -07:00
Eddie Hung
f46ac1df9f
Be mindful that sigmap(wire) could have dupes when checking \init
2019-10-02 16:08:46 -07:00
Eddie Hung
265a655ef9
Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf
2019-10-02 12:43:35 -07:00
Clifford Wolf
45e4c040d7
Add "check -mapped"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-02 13:35:03 +02:00
Eddie Hung
edc3780723
techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias
2019-09-30 17:20:12 -07:00
Eddie Hung
1b96d29174
No need to punch ports at all
2019-09-30 17:02:20 -07:00
Eddie Hung
390b960c8c
Resolve FIXME on calling proc just once
2019-09-30 16:37:29 -07:00
Eddie Hung
e529872b01
Remove need for $currQ port connection
2019-09-30 16:33:40 -07:00
Eddie Hung
f2f19df2d4
Add -select option to aigmap
2019-09-30 15:26:29 -07:00
Eddie Hung
e0aa772663
Add comment
2019-09-30 15:19:02 -07:00
Eddie Hung
a6994c5f16
scc call on active module module only, plus cleanup
2019-09-30 12:57:19 -07:00
Eddie Hung
8684b58bed
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-30 12:29:35 -07:00
Eddie Hung
a274b7cc86
Update doc for equiv_opt
2019-09-30 10:59:56 -07:00
Miodrag Milanović
0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in
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Open aig frontend as binary file
2019-09-30 17:49:23 +02:00
Clifford Wolf
0d28e45dcb
Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2sync
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equiv_opt to call async2sync when not -multiclock like SymbiYosys
2019-09-30 17:04:21 +02:00
Clifford Wolf
10e57f3880
Fix $dlatch handling in async2sync
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-30 14:58:23 +02:00
Eddie Hung
1123c09588
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 19:39:12 -07:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp
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DSP inference for Xilinx (improved for ice40, initial support for ecp5)
2019-09-29 11:26:22 -07:00
Eddie Hung
5a4011e8c9
Fix "scc" call inside abc9 to consider all wires
2019-09-29 09:58:00 -07:00
Miodrag Milanovic
3f70c1fd26
Open aig frontend as binary file
2019-09-29 13:22:11 +02:00
Eddie Hung
79b6edb639
Big rework; flop info now mostly in cells_sim.v
2019-09-28 23:48:17 -07:00
Eddie Hung
313d2478e9
Split ABC9 based on clocking only, add "abc_mergeability" attr for en
2019-09-27 18:41:04 -07:00
Eddie Hung
fe722b737c
Add -select option to aigmap
2019-09-27 17:44:01 -07:00
Eddie Hung
8f5710c464
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-27 15:14:31 -07:00
Eddie Hung
a39505e329
equiv_opt to call async2sync when not -multiclock like SymbiYosys
2019-09-27 12:59:10 -07:00
Eddie Hung
aebbfffd71
Ooops AREG and BREG to default to -1
2019-09-27 11:57:53 -07:00
Marcin Kościelnicki
fd0e3a2c43
Fix _TECHMAP_REMOVEINIT_ handling.
...
Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.
Fixes the problem identified in #1396 .
2019-09-27 18:34:12 +02:00
Eddie Hung
26657037b8
Update doc with max cascade chain of 20
2019-09-26 14:31:02 -07:00
Eddie Hung
5b9deef10d
Do not always zero out C (e.g. during cascade breaks)
2019-09-26 13:59:05 -07:00
Eddie Hung
95f0dd57df
Update doc
2019-09-26 13:44:41 -07:00
Eddie Hung
58f31096ab
Zero out ports
2019-09-26 13:40:38 -07:00
Eddie Hung
af59856ba1
xilinx_dsp_cascade to also cascade AREG and BREG
2019-09-26 13:29:18 -07:00
Eddie Hung
832216dab0
Try recursive pmgen for P cascade
2019-09-26 12:09:57 -07:00
Eddie Hung
bd8661e024
CREG to check for \keep
2019-09-26 10:32:01 -07:00
Eddie Hung
c0bb1d22e8
Remove newline
2019-09-26 10:31:55 -07:00
Eddie Hung
f1de93edf5
Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed)
2019-09-25 22:58:03 -07:00
Eddie Hung
cd8a640989
Reject if (* init *) present
2019-09-25 18:21:08 -07:00
Eddie Hung
aeb1539818
Rework xilinx_dsp postAdd for new wreduce call
2019-09-25 17:22:30 -07:00
Eddie Hung
5f8917c984
Fix memory issue since SigSpec& could be invalidated
2019-09-25 16:45:51 -07:00
Eddie Hung
486dd7c483
unextend only used in init
2019-09-25 14:05:59 -07:00
Eddie Hung
53ea5daa42
Call 'wreduce' after mul2dsp to avoid unextend()
2019-09-25 14:04:36 -07:00
Clifford Wolf
b432c9b44b
Improve "portlist" command
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-25 09:20:38 +02:00
Clifford Wolf
6c427d36dd
Add "portlist" command
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-24 18:08:59 +02:00
Eddie Hung
44374b1b2b
"abc_padding" attr for blackbox outputs that were padded, remove them later
2019-09-23 21:58:40 -07:00
Eddie Hung
e556d48d45
Set [AB]CASCREG to legal values
2019-09-23 16:00:11 -07:00
Eddie Hung
b824a56cde
Comment to explain separating CREG packing
2019-09-23 13:58:10 -07:00
Eddie Hung
15dfbc8125
Separate out CREG packing into new pattern, to avoid conflict with PREG
2019-09-23 13:27:10 -07:00
Eddie Hung
26a6c55665
Move log_debug("\n") later
2019-09-23 13:27:00 -07:00
Eddie Hung
d0dbbc2605
Move unextend initialisation later
2019-09-23 13:26:34 -07:00
Eddie Hung
a67af3d5e5
Use new port() overload once more
2019-09-23 13:00:44 -07:00
Eddie Hung
bcee87a457
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-23 10:58:28 -07:00
N. Engelhardt
3bed4cb18a
fix show command for macos
2019-09-23 17:47:05 +02:00
Eddie Hung
ec08a031b5
Revert abc9.cc
2019-09-20 17:52:23 -07:00
Eddie Hung
72ce06909e
Trim mismatched connection to be same (smallest) size
2019-09-20 17:51:36 -07:00
Eddie Hung
567e5f0aa7
Fix first testcase in #1391
2019-09-20 17:51:27 -07:00