mirror of https://github.com/YosysHQ/yosys.git
Set [AB]CASCREG to legal values
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@ -275,7 +275,6 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
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log_debug("postAddMux: %s\n", log_id(st.postAddMux, "--"));
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log_debug("ffP: %s %s %s\n", log_id(st.ffP, "--"), log_id(st.ffPcemux, "--"), log_id(st.ffPrstmux, "--"));
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log_debug("overflow: %s\n", log_id(st.overflow, "--"));
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log_debug("\n");
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Cell *cell = st.dsp;
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@ -410,9 +409,12 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
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if (st.ffA1) {
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f(A, st.ffA1, st.ffA1cemux, st.ffA1cepol, ID(CEA1), st.ffA1rstmux, st.ffArstpol, IdString());
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cell->setParam(ID(AREG), 2);
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cell->setParam(ID(ACASCREG), 2);
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}
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else
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else {
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cell->setParam(ID(AREG), 1);
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cell->setParam(ID(ACASCREG), 1);
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}
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}
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if (st.ffB2) {
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SigSpec &B = cell->connections_.at(ID(B));
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@ -421,9 +423,12 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
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if (st.ffB1) {
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f(B, st.ffB1, st.ffB1cemux, st.ffB1cepol, ID(CEB1), st.ffB1rstmux, st.ffBrstpol, IdString());
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cell->setParam(ID(BREG), 2);
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cell->setParam(ID(BCASCREG), 2);
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}
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else
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else {
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cell->setParam(ID(BREG), 1);
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cell->setParam(ID(BCASCREG), 1);
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}
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}
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if (st.ffD) {
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SigSpec &D = cell->connections_.at(ID(D));
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@ -469,9 +474,8 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
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if (st.ffP)
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log(" ffP:%s", log_id(st.ffP));
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log("\n");
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}
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log("\n");
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SigSpec P = st.sigP;
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if (GetSize(P) < 48)
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@ -624,7 +628,7 @@ struct XilinxDspPass : public Pass {
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xilinx_dsp_cascade_pm pm(module, module->selected_cells());
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pm.run_xilinx_dsp_cascadeP();
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//pm.run_xilinx_dsp_cascadeAB();
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break;
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break;
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} while (did_something);
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}
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}
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