mirror of https://github.com/YosysHQ/yosys.git
Separate out CREG packing into new pattern, to avoid conflict with PREG
This commit is contained in:
Eddie Hung
parent
26a6c55665
commit
15dfbc8125
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@ -22,8 +22,9 @@ $(eval $(call add_extra_objs,passes/pmgen/ice40_wrapcarry_pm.h))
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# --------------------------------------
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OBJS += passes/pmgen/xilinx_dsp.o
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passes/pmgen/xilinx_dsp.o: passes/pmgen/xilinx_dsp_pm.h passes/pmgen/xilinx_dsp_cascade_pm.h
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passes/pmgen/xilinx_dsp.o: passes/pmgen/xilinx_dsp_pm.h passes/pmgen/xilinx_dsp_CREG_pm.h passes/pmgen/xilinx_dsp_cascade_pm.h
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$(eval $(call add_extra_objs,passes/pmgen/xilinx_dsp_pm.h))
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$(eval $(call add_extra_objs,passes/pmgen/xilinx_dsp_CREG_pm.h))
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$(eval $(call add_extra_objs,passes/pmgen/xilinx_dsp_cascade_pm.h))
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# --------------------------------------
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@ -27,6 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
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bool did_something;
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#include "passes/pmgen/xilinx_dsp_pm.h"
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#include "passes/pmgen/xilinx_dsp_CREG_pm.h"
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#include "passes/pmgen/xilinx_dsp_cascade_pm.h"
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static Cell* addDsp(Module *module) {
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@ -63,7 +64,7 @@ static Cell* addDsp(Module *module) {
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return cell;
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}
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void pack_xilinx_simd(Module *module, const std::vector<Cell*> &selected_cells)
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void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
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{
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std::deque<Cell*> simd12_add, simd12_sub;
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std::deque<Cell*> simd24_add, simd24_sub;
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@ -255,21 +256,18 @@ void pack_xilinx_simd(Module *module, const std::vector<Cell*> &selected_cells)
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g24(simd24_sub);
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}
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void pack_xilinx_dsp(xilinx_dsp_pm &pm)
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void xilinx_dsp_pack(xilinx_dsp_pm &pm)
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{
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auto &st = pm.st_xilinx_dsp_pack;
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log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp));
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log_debug("\n");
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log_debug("preAdd: %s\n", log_id(st.preAdd, "--"));
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log_debug("ffAD: %s %s %s\n", log_id(st.ffAD, "--"), log_id(st.ffADcemux, "--"), log_id(st.ffADrstmux, "--"));
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log_debug("ffA2: %s %s %s\n", log_id(st.ffA2, "--"), log_id(st.ffA2cemux, "--"), log_id(st.ffA2rstmux, "--"));
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log_debug("ffA1: %s %s %s\n", log_id(st.ffA1, "--"), log_id(st.ffA1cemux, "--"), log_id(st.ffA1rstmux, "--"));
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log_debug("ffB2: %s %s %s\n", log_id(st.ffB2, "--"), log_id(st.ffB2cemux, "--"), log_id(st.ffB2rstmux, "--"));
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log_debug("ffB1: %s %s %s\n", log_id(st.ffB1, "--"), log_id(st.ffB1cemux, "--"), log_id(st.ffB1rstmux, "--"));
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log_debug("ffC: %s %s %s\n", log_id(st.ffC, "--"), log_id(st.ffCcemux, "--"), log_id(st.ffCrstmux, "--"));
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log_debug("ffD: %s %s %s\n", log_id(st.ffD, "--"), log_id(st.ffDcemux, "--"), log_id(st.ffDrstmux, "--"));
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log_debug("dsp: %s\n", log_id(st.dsp, "--"));
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log_debug("ffM: %s %s %s\n", log_id(st.ffM, "--"), log_id(st.ffMcemux, "--"), log_id(st.ffMrstmux, "--"));
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@ -277,6 +275,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
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log_debug("postAddMux: %s\n", log_id(st.postAddMux, "--"));
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log_debug("ffP: %s %s %s\n", log_id(st.ffP, "--"), log_id(st.ffPcemux, "--"), log_id(st.ffPrstmux, "--"));
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log_debug("overflow: %s\n", log_id(st.overflow, "--"));
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log_debug("\n");
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Cell *cell = st.dsp;
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@ -426,12 +425,6 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
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else
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cell->setParam(ID(BREG), 1);
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}
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if (st.ffC) {
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SigSpec &C = cell->connections_.at(ID(C));
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f(C, st.ffC, st.ffCcemux, st.ffCcepol, ID(CEC), st.ffCrstmux, st.ffCrstpol, ID(RSTC));
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pm.add_siguser(C, cell);
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cell->setParam(ID(CREG), 1);
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}
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if (st.ffD) {
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SigSpec &D = cell->connections_.at(ID(D));
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f(D, st.ffD, st.ffDcemux, st.ffDcepol, ID(CED), st.ffDrstmux, st.ffDrstpol, ID(RSTD));
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@ -468,9 +461,6 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
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log(" ffB1:%s", log_id(st.ffB1));
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}
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if (st.ffC)
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log(" ffC:%s", log_id(st.ffC));
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if (st.ffD)
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log(" ffD:%s", log_id(st.ffD));
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@ -491,6 +481,76 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
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pm.blacklist(cell);
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}
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void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
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{
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auto &st = pm.st_xilinx_dsp_packC;
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log_debug("Analysing %s.%s for Xilinx DSP packing (CREG).\n", log_id(pm.module), log_id(st.dsp));
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log_debug("ffC: %s %s %s\n", log_id(st.ffC, "--"), log_id(st.ffCcemux, "--"), log_id(st.ffCrstmux, "--"));
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log_debug("\n");
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Cell *cell = st.dsp;
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if (st.clock != SigBit())
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{
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cell->setPort(ID(CLK), st.clock);
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auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) {
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SigSpec D = ff->getPort(ID(D));
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SigSpec Q = pm.sigmap(ff->getPort(ID(Q)));
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if (!A.empty())
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A.replace(Q, D);
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if (rstmux) {
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SigSpec Y = rstmux->getPort(ID(Y));
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SigSpec AB = rstmux->getPort(rstpol ? ID(A) : ID(B));
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if (!A.empty())
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A.replace(Y, AB);
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if (rstport != IdString()) {
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SigSpec S = rstmux->getPort(ID(S));
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cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S));
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}
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}
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else if (rstport != IdString())
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cell->setPort(rstport, State::S0);
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if (cemux) {
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SigSpec Y = cemux->getPort(ID(Y));
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SigSpec BA = cemux->getPort(cepol ? ID(B) : ID(A));
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SigSpec S = cemux->getPort(ID(S));
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if (!A.empty())
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A.replace(Y, BA);
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cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S));
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}
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else
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cell->setPort(ceport, State::S1);
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for (auto c : Q.chunks()) {
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auto it = c.wire->attributes.find(ID(init));
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if (it == c.wire->attributes.end())
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continue;
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for (int i = c.offset; i < c.offset+c.width; i++) {
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log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
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it->second[i] = State::Sx;
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}
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}
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};
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if (st.ffC) {
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SigSpec &C = cell->connections_.at(ID(C));
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f(C, st.ffC, st.ffCcemux, st.ffCcepol, ID(CEC), st.ffCrstmux, st.ffCrstpol, ID(RSTC));
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pm.add_siguser(C, cell);
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cell->setParam(ID(CREG), 1);
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}
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log(" clock: %s (%s)", log_signal(st.clock), "posedge");
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if (st.ffC)
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log(" ffC:%s", log_id(st.ffC));
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log("\n");
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}
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pm.blacklist(cell);
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}
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struct XilinxDspPass : public Pass {
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XilinxDspPass() : Pass("xilinx_dsp", "Xilinx: pack resources into DSPs") { }
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void help() YS_OVERRIDE
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@ -540,17 +600,23 @@ struct XilinxDspPass : public Pass {
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules()) {
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pack_xilinx_simd(module, module->selected_cells());
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xilinx_simd_pack(module, module->selected_cells());
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xilinx_dsp_pm pm(module, module->selected_cells());
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pm.run_xilinx_dsp_pack(pack_xilinx_dsp);
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{
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xilinx_dsp_pm pm(module, module->selected_cells());
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pm.run_xilinx_dsp_pack(xilinx_dsp_pack);
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}
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{
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xilinx_dsp_CREG_pm pm(module, module->selected_cells());
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pm.run_xilinx_dsp_packC(xilinx_dsp_packC);
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}
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do {
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did_something = false;
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xilinx_dsp_cascade_pm pmc(module, module->selected_cells());
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pmc.run_xilinx_dsp_cascadeP();
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//pmc.run_xilinx_dsp_cascadeAB();
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break;
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xilinx_dsp_cascade_pm pm(module, module->selected_cells());
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pm.run_xilinx_dsp_cascadeP();
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//pm.run_xilinx_dsp_cascadeAB();
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break;
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} while (did_something);
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}
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}
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@ -4,11 +4,11 @@ udata <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigBit> clock
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state <SigSpec> sigA sigB sigC sigD sigM sigP
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state <IdString> postAddAB postAddMuxAB
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state <bool> ffA1cepol ffA2cepol ffADcepol ffB1cepol ffB2cepol ffCcepol ffDcepol ffMcepol ffPcepol
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state <bool> ffArstpol ffADrstpol ffBrstpol ffCrstpol ffDrstpol ffMrstpol ffPrstpol
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state <bool> ffA1cepol ffA2cepol ffADcepol ffB1cepol ffB2cepol ffDcepol ffMcepol ffPcepol
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state <bool> ffArstpol ffADrstpol ffBrstpol ffDrstpol ffMrstpol ffPrstpol
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state <Cell*> ffAD ffADcemux ffADrstmux ffA1 ffA1cemux ffA1rstmux ffA2 ffA2cemux ffA2rstmux
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state <Cell*> ffB1 ffB1cemux ffB1rstmux ffB2 ffB2cemux ffB2rstmux ffC ffCcemux ffCrstmux
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state <Cell*> ffB1 ffB1cemux ffB1rstmux ffB2 ffB2cemux ffB2rstmux
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state <Cell*> ffD ffDcemux ffDrstmux ffM ffMcemux ffMrstmux ffP ffPcemux ffPrstmux
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// subpattern
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@ -24,7 +24,7 @@ match dsp
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select dsp->type.in(\DSP48E1)
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endmatch
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code sigA sigB sigC sigD sigM
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code sigA sigB sigC sigD sigM clock
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unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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@ -54,6 +54,8 @@ code sigA sigB sigC sigD sigM
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}
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else
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sigM = P;
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clock = port(dsp, \CLK, SigBit());
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endcode
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code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock
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@ -326,26 +328,6 @@ code sigC
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sigC = port(postAddMux, postAddMuxAB == \A ? \B : \A);
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endcode
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code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
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if (param(dsp, \CREG).as_int() == 0 && sigC != sigP) {
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argQ = sigC;
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subpattern(in_dffe);
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if (dff) {
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ffC = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffCrstmux = dffrstmux;
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ffCrstpol = dffrstpol;
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}
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if (dffcemux) {
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ffCcemux = dffcemux;
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ffCcepol = dffcepol;
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}
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sigC = dffD;
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}
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}
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endcode
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match overflow
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if ffP
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if param(dsp, \USE_PATTERN_DETECT, Const("NO_PATDET")).decode_string() == "NO_PATDET"
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@ -0,0 +1,178 @@
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pattern xilinx_dsp_packC
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigBit> clock
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state <SigSpec> sigC sigP
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state <bool> ffCcepol ffCrstpol
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state <Cell*> ffC ffCcemux ffCrstmux
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// subpattern
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state <SigSpec> argQ argD
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state <bool> ffcepol ffrstpol
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state <int> ffoffset
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff dffcemux dffrstmux
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udata <bool> dffcepol dffrstpol
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match dsp
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select dsp->type.in(\DSP48E1)
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select param(dsp, \CREG, 1).as_int() == 0
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select nusers(port(dsp, \C, SigSpec())) > 1
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endmatch
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code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC sigP clock
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unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove non-const sign bit
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if (sig[i].wire)
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++i;
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return sig.extract(0, i);
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};
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sigC = unextend(port(dsp, \C, SigSpec()));
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SigSpec P = port(dsp, \P);
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if (param(dsp, \USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") {
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// Only care about those bits that are used
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int i;
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for (i = 0; i < GetSize(P); i++) {
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if (nusers(P[i]) <= 1)
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break;
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sigP.append(P[i]);
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}
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log_assert(nusers(P.extract_end(i)) <= 1);
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}
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else
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sigP = P;
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if (sigC == sigP)
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reject;
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clock = port(dsp, \CLK, SigBit());
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argQ = sigC;
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subpattern(in_dffe);
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if (dff) {
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ffC = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffCrstmux = dffrstmux;
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ffCrstpol = dffrstpol;
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}
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if (dffcemux) {
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ffCcemux = dffcemux;
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ffCcepol = dffcepol;
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}
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sigC = dffD;
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}
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endcode
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code
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if (ffC)
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accept;
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endcode
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// #######################
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subpattern in_dffe
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arg argD argQ clock
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code
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dff = nullptr;
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for (auto c : argQ.chunks()) {
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if (!c.wire)
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reject;
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if (c.wire->get_bool_attribute(\keep))
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reject;
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}
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endcode
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match ff
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select ff->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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slice offset GetSize(port(ff, \D))
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index <SigBit> port(ff, \Q)[offset] === argQ[0]
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// Check that the rest of argQ is present
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filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
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filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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set ffoffset offset
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endmatch
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code argQ argD
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{
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if (clock != SigBit() && port(ff, \CLK) != clock)
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reject;
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SigSpec Q = port(ff, \Q);
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dff = ff;
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dffclock = port(ff, \CLK);
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dffD = argQ;
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argD = port(ff, \D);
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argQ = Q;
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dffD.replace(argQ, argD);
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// Only search for ffrstmux if dffD only
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// has two (ff, ffrstmux) users
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if (nusers(dffD) > 2)
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argD = SigSpec();
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}
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endcode
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match ffrstmux
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if !argD.empty()
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select ffrstmux->type.in($mux)
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index <SigSpec> port(ffrstmux, \Y) === argD
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choice <IdString> BA {\B, \A}
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// DSP48E1 only supports reset to zero
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select port(ffrstmux, BA).is_fully_zero()
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define <bool> pol (BA == \B)
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set ffrstpol pol
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semioptional
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endmatch
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code argD
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if (ffrstmux) {
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dffrstmux = ffrstmux;
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dffrstpol = ffrstpol;
|
||||
argD = port(ffrstmux, ffrstpol ? \A : \B);
|
||||
dffD.replace(port(ffrstmux, \Y), argD);
|
||||
|
||||
// Only search for ffcemux if argQ has at
|
||||
// least 3 users (ff, <upstream>, ffrstmux) and
|
||||
// dffD only has two (ff, ffrstmux)
|
||||
if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
|
||||
argD = SigSpec();
|
||||
}
|
||||
else
|
||||
dffrstmux = nullptr;
|
||||
endcode
|
||||
|
||||
match ffcemux
|
||||
if !argD.empty()
|
||||
select ffcemux->type.in($mux)
|
||||
index <SigSpec> port(ffcemux, \Y) === argD
|
||||
choice <IdString> AB {\A, \B}
|
||||
index <SigSpec> port(ffcemux, AB) === argQ
|
||||
define <bool> pol (AB == \A)
|
||||
set ffcepol pol
|
||||
semioptional
|
||||
endmatch
|
||||
|
||||
code argD
|
||||
if (ffcemux) {
|
||||
dffcemux = ffcemux;
|
||||
dffcepol = ffcepol;
|
||||
argD = port(ffcemux, ffcepol ? \B : \A);
|
||||
dffD.replace(port(ffcemux, \Y), argD);
|
||||
}
|
||||
else
|
||||
dffcemux = nullptr;
|
||||
endcode
|
||||
Loading…
Reference in New Issue