mirror of https://github.com/YosysHQ/yosys.git
Move unextend initialisation later
This commit is contained in:
parent
a67af3d5e5
commit
d0dbbc2605
|
@ -3,19 +3,6 @@ pattern xilinx_dsp_cascadeP
|
|||
udata <std::function<SigSpec(const SigSpec&)>> unextend
|
||||
state <SigSpec> sigC
|
||||
|
||||
code
|
||||
unextend = [](const SigSpec &sig) {
|
||||
int i;
|
||||
for (i = GetSize(sig)-1; i > 0; i--)
|
||||
if (sig[i] != sig[i-1])
|
||||
break;
|
||||
// Do not remove non-const sign bit
|
||||
if (sig[i].wire)
|
||||
++i;
|
||||
return sig.extract(0, i);
|
||||
};
|
||||
endcode
|
||||
|
||||
match dsp_pcin
|
||||
select dsp_pcin->type.in(\DSP48E1)
|
||||
select !param(dsp_pcin, \CREG, State::S1).as_bool()
|
||||
|
@ -25,6 +12,16 @@ match dsp_pcin
|
|||
endmatch
|
||||
|
||||
code sigC
|
||||
unextend = [](const SigSpec &sig) {
|
||||
int i;
|
||||
for (i = GetSize(sig)-1; i > 0; i--)
|
||||
if (sig[i] != sig[i-1])
|
||||
break;
|
||||
// Do not remove non-const sign bit
|
||||
if (sig[i].wire)
|
||||
++i;
|
||||
return sig.extract(0, i);
|
||||
};
|
||||
sigC = unextend(port(dsp_pcin, \C));
|
||||
endcode
|
||||
|
||||
|
|
Loading…
Reference in New Issue