mirror of https://github.com/YosysHQ/yosys.git
Try recursive pmgen for P cascade
This commit is contained in:
Eddie Hung
parent
84825f9378
commit
832216dab0
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@ -1,100 +1,133 @@
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pattern xilinx_dsp_cascadeP
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigSpec> sigC
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udata <vector<std::pair<Cell*,bool>>> chain longest_chain
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match dsp_pcin
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select dsp_pcin->type.in(\DSP48E1)
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select !param(dsp_pcin, \CREG, State::S1).as_bool()
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select port(dsp_pcin, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")
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select nusers(port(dsp_pcin, \C, SigSpec())) > 1
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select nusers(port(dsp_pcin, \PCIN, SigSpec())) == 0
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endmatch
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code sigC
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unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove non-const sign bit
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if (sig[i].wire)
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++i;
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return sig.extract(0, i);
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};
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sigC = unextend(port(dsp_pcin, \C));
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code
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#define MAX_DSP_CASCADE 20
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endcode
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match dsp_pcout
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select dsp_pcout->type.in(\DSP48E1)
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select nusers(port(dsp_pcout, \P, SigSpec())) > 1
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select nusers(port(dsp_pcout, \PCOUT, SigSpec())) <= 1
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index <SigBit> port(dsp_pcout, \P)[0] === sigC[0]
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filter GetSize(port(dsp_pcin, \P)) >= GetSize(sigC)
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filter port(dsp_pcout, \P).extract(0, GetSize(sigC)) == sigC
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optional
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endmatch
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match dsp_pcout_shift17
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if !dsp_pcout
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select dsp_pcout_shift17->type.in(\DSP48E1)
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select nusers(port(dsp_pcout_shift17, \P, SigSpec())) > 1
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select nusers(port(dsp_pcout_shift17, \PCOUT, SigSpec())) <= 1
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index <SigBit> port(dsp_pcout_shift17, \P)[17] === sigC[0]
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filter GetSize(port(dsp_pcout_shift17, \P)) >= GetSize(sigC)+17
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filter port(dsp_pcout_shift17, \P).extract(17, GetSize(sigC)) == sigC
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match first
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select first->type.in(\DSP48E1)
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select port(first, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("000")
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select nusers(port(first, \PCOUT, SigSpec())) <= 1
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endmatch
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code
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Cell *dsp;
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if (dsp_pcout)
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dsp = dsp_pcout;
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else if (dsp_pcout_shift17)
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dsp = dsp_pcout_shift17;
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else log_abort();
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longest_chain.clear();
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chain.emplace_back(first, false);
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subpattern(tail);
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finally
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chain.pop_back();
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log_assert(chain.empty());
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if (GetSize(longest_chain) > 1) {
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Cell *dsp = longest_chain.front().first;
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dsp_pcin->setPort(ID(C), Const(0, 48));
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for (int i = 1; i < GetSize(longest_chain); i++) {
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Cell *dsp_pcin = longest_chain[i].first;
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bool shift17 = longest_chain[i].second;
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Wire *cascade = module->addWire(NEW_ID, 48);
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dsp_pcin->setPort(ID(PCIN), cascade);
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dsp->setPort(ID(PCOUT), cascade);
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add_siguser(cascade, dsp_pcin);
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add_siguser(cascade, dsp);
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dsp_pcin->setPort(ID(C), Const(0, 48));
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SigSpec opmode = port(dsp_pcin, \OPMODE, Const(0, 7));
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if (dsp_pcout)
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opmode[6] = State::S0;
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else if (dsp_pcout_shift17)
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opmode[6] = State::S1;
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else log_abort();
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if (i % MAX_DSP_CASCADE > 0) {
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Wire *cascade = module->addWire(NEW_ID, 48);
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dsp_pcin->setPort(ID(PCIN), cascade);
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dsp->setPort(ID(PCOUT), cascade);
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add_siguser(cascade, dsp_pcin);
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add_siguser(cascade, dsp);
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opmode[5] = State::S0;
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opmode[4] = State::S1;
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dsp_pcin->setPort(\OPMODE, opmode);
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SigSpec opmode = port(dsp_pcin, \OPMODE, Const(0, 7));
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if (shift17)
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opmode[6] = State::S1;
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else
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opmode[6] = State::S0;
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log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
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opmode[5] = State::S0;
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opmode[4] = State::S1;
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dsp_pcin->setPort(\OPMODE, opmode);
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if (nusers(port(dsp_pcin, \PCOUT, SigSpec())) > 1) {
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log_debug(" Saturated PCIN/PCOUT on %s\n", log_id(dsp_pcin));
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blacklist(dsp_pcin);
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}
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if (nusers(port(dsp, \PCIN, SigSpec())) > 1) {
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log_debug(" Saturated PCIN/PCOUT on %s\n", log_id(dsp));
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blacklist(dsp_pcout);
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log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
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}
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else {
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log_debug("Blocking PCOUT -> PCIN cascade for %s -> %s (exceeds max: %d)\n", log_id(dsp), log_id(dsp_pcin), MAX_DSP_CASCADE);
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}
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dsp = dsp_pcin;
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}
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did_something = true;
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accept;
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}
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endcode
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did_something = true;
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accept;
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// ------------------------------------------------------------------
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subpattern tail
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arg first
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match next
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select next->type.in(\DSP48E1)
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select !param(next, \CREG, State::S1).as_bool()
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select port(next, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")
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select nusers(port(next, \C, SigSpec())) > 1
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select nusers(port(next, \PCIN, SigSpec())) == 0
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index <SigBit> port(next, \C)[0] === port(chain.back().first, \P)[0]
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semioptional
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endmatch
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match next_shift17
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if !next_shift17
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select next_shift17->type.in(\DSP48E1)
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select !param(next_shift17, \CREG, State::S1).as_bool()
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select port(next_shift17, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")
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select nusers(port(next_shift17, \C, SigSpec())) > 1
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select nusers(port(next_shift17, \PCIN, SigSpec())) == 0
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index <SigBit> port(next_shift17, \C)[0] === port(chain.back().first, \P)[17]
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semioptional
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endmatch
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code next
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if (!next)
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next = next_shift17;
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if (next) {
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chain.emplace_back(next, next_shift17);
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auto unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove non-const sign bit
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if (sig[i].wire)
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++i;
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return sig.extract(0, i);
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};
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SigSpec sigC = unextend(port(next, \C));
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// TODO: Cannot use 'reject' since semioptional
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if (next_shift17) {
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if (GetSize(sigC)+17 <= GetSize(port(chain.back().first, \P)) &&
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port(chain.back().first, \P).extract(17, GetSize(sigC)) != sigC)
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subpattern(tail);
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}
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else {
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if (GetSize(sigC) <= GetSize(port(chain.back().first, \P)) &&
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port(chain.back().first, \P).extract(0, GetSize(sigC)) != sigC)
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subpattern(tail);
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}
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} else {
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if (GetSize(chain) > GetSize(longest_chain))
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longest_chain = chain;
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}
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finally
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if (next)
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chain.pop_back();
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endcode
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// ##########
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pattern xilinx_dsp_cascadeAB
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigBit> clock
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state <SigSpec> sigA sigB
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@ -113,8 +146,13 @@ udata <SigBit> dffclock
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udata <Cell*> dff dffcemux dffrstmux
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udata <bool> dffcepol dffrstpol
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code
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unextend = [](const SigSpec &sig) {
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match dspD
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select dspD->type.in(\DSP48E1)
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select (param(dspD, \A_INPUT, Const("DIRECT")).decode_string() == "DIRECT" && nusers(port(dspD, \A, SigSpec())) > 1 && nusers(port(dspD, \ACIN, SigSpec())) == 0) || (param(dspD, \B_INPUT, Const("DIRECT")).decode_string() == "DIRECT" && nusers(port(dspD, \B, SigSpec())) > 1 && nusers(port(dspD, \BCIN, SigSpec())) == 0)
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endmatch
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code sigA sigB
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auto unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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@ -124,14 +162,6 @@ code
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++i;
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return sig.extract(0, i);
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};
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endcode
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match dspD
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select dspD->type.in(\DSP48E1)
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select (param(dspD, \A_INPUT, Const("DIRECT")).decode_string() == "DIRECT" && nusers(port(dspD, \A, SigSpec())) > 1 && nusers(port(dspD, \ACIN, SigSpec())) == 0) || (param(dspD, \B_INPUT, Const("DIRECT")).decode_string() == "DIRECT" && nusers(port(dspD, \B, SigSpec())) > 1 && nusers(port(dspD, \BCIN, SigSpec())) == 0)
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endmatch
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code sigA sigB
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if (param(dspD, \A_INPUT, Const("DIRECT")).decode_string() == "DIRECT")
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sigA = unextend(port(dspD, \A));
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if (param(dspD, \B_INPUT, Const("DIRECT")).decode_string() == "DIRECT")
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