riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Ooops AREG and BREG to default to -1

This commit is contained in:
Eddie Hung 2019-09-27 11:57:53 -07:00
parent 26657037b8
commit aebbfffd71
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
passes/pmgen/xilinx_dsp_cascade.pmg
View File

@ -146,7 +146,7 @@ code next
endcode
code argQ clock AREG
AREG = 0;
AREG = -1;
if (next) {
Cell *prev = std::get<0>(chain.back());
if (param(prev, \AREG, 2).as_int() > 0 &&
@ -175,7 +175,7 @@ reject_AREG: ;
endcode
code argQ clock BREG
BREG = 0;
BREG = -1;
if (next) {
Cell *prev = std::get<0>(chain.back());
if (param(prev, \BREG, 2).as_int() > 0 &&