d453e6477d
[FPGA-Verilog] Bug fix
2021-10-02 22:32:57 -07:00
02af633acd
[FPGA-Verilog] Fixed several bugs in testbench generator which caused iVerilog errors
2021-10-02 22:14:15 -07:00
fa7e168137
[FPGA-Verilog] Now testbench generator connects global shift register clocks to FPGA ports
2021-10-02 22:08:14 -07:00
76d58ebaa0
[FPGA-Verilog] Move clock generator to generic stimuli and shift register clock period is auto tuned by programming clock period
2021-10-02 21:48:10 -07:00
54ec74d8d2
[FPGA-Verilog] Bug fix in code generator
2021-10-02 17:31:37 -07:00
32fc0a1692
[FPGA-Verilog] Upgrading verilog testbench generator for QuickLogic memory bank using BL/WL shift register
2021-10-02 17:25:27 -07:00
f686dd1f60
[FPGA-Bitstream] Do not reverse for now. Previous solution looks correct
2021-10-01 23:12:38 -07:00
198517a898
[FPGA-Bitstream] Bug fix on bitstream sequence for QuickLogic memory bank using shift registers
2021-10-01 19:59:50 -07:00
2de6be44d6
[Engine] Fixed a critical bug which causes bitstream wrong for QuickLogic memory bank when fast configuration is enabled
2021-10-01 18:27:42 -07:00
477c1cd062
[Engine] Fixed a critical bug which causes undriven BL/WLs between shift register banks and child modules at the top-level module
2021-10-01 17:38:26 -07:00
977d81679d
[Engine] Upgrade check codes for WL CCFF
2021-10-01 17:23:10 -07:00
9e5debabe1
[FPGA-Bitstream] Enable fast configuration for QuickLogic memory banks
2021-10-01 16:23:38 -07:00
4f7ab01bf5
[FPGA-Bitstream] Reworked the bitstream writer to dump BL/WL words separately
2021-10-01 15:47:13 -07:00
2bd2788e77
[Engine] Upgrading testbench generator to support QuickLogic memory bank with shift registers
2021-10-01 11:23:40 -07:00
cf96d9ff01
[Engine] Add programming shift register clock to internal global port data structure
2021-10-01 11:05:31 -07:00
7b010ba0f4
[Engine] Support programming shift register clock in XML syntax
2021-10-01 11:00:38 -07:00
96828e456a
[FPGA-Bitstream] Fixed a critical bug which cause reshaping bitstream wrong
2021-09-30 22:07:46 -07:00
4bdff1554d
[Engine] Fixed a critical bug which cause BL/WL sharing in shift-register-based memory bank broken
2021-09-30 21:20:56 -07:00
33972fc0ec
[FPGA-Bitstream] Upgraded bitstream writer to support QuickLogic memory bank using shift registers
2021-09-30 21:05:41 -07:00
4526133089
[FPGA-Bitstream] Add a new data structure that stores fabric bitstream for memory bank using shift registers
2021-09-30 17:01:02 -07:00
43c569b612
[FPGA-Bitstream] Encapusulate the data structur storing memory bank fabric bitstream for flatten BL/WL into an object
2021-09-30 14:47:21 -07:00
4d8019b7c1
[FPGA-Bitstream] Bug fix in bitstream generator for shift-register-based memory bank
2021-09-29 22:32:45 -07:00
2d4c200d58
[FPGA-Verilog] Now FPGA-Verilog can output shift register bank netlists
2021-09-29 20:56:02 -07:00
f456c7e236
[Engine] Add a new API to the MemoryBankShiftRegisterBank to access all the unique modules
2021-09-29 20:34:25 -07:00
b87b7a99c5
[Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators
2021-09-29 20:21:46 -07:00
8f0ae937bc
[Engine] Upgraded fabric generator to support single shift register bank per configuration region for QuickLogic memory bank
2021-09-29 16:57:49 -07:00
ac6268d9ae
[Engine] Bug fix on compilation errors
2021-09-29 16:24:36 -07:00
c5ae93f177
[Engine] Upgraded fabric generator to support shifter register banks in Quicklogic memory bank
2021-09-29 16:17:40 -07:00
5da8f1db73
[Engine] Upgrading fabric generator to connect nets between top module and BL/WL shift register modules
2021-09-28 23:27:47 -07:00
7723e00e6c
[Engine] Adding the function that builds a shift register module for BL/WLs
2021-09-28 22:49:24 -07:00
834bdd2b07
[Engine] Updating fabric generator to support BL/WL shift registers. Still WIP
2021-09-28 17:29:03 -07:00
afd03d7eb7
[Engine] Add more check codes for the CCFF circuit model used by BL/WL shift registers
2021-09-28 15:56:07 -07:00
0d72e115ac
[Engine] Bug fix for the undriven WLR nets in top-level modules
2021-09-28 11:53:38 -07:00
33e9b27cb8
[Engine] Fixed a critical bug when building final bitstream, which may cause loss when merging BLs
2021-09-25 20:22:27 -07:00
29c351f5a4
[Engine] Bug fix in estimating the configuration cycles for Verilog testbench generator
2021-09-25 19:34:21 -07:00
e06ac11630
[Engine] Bug fix
2021-09-25 19:21:16 -07:00
3cf31f1565
[Engine] Fixed bugs
2021-09-25 18:22:55 -07:00
a56d1f4fdb
[FPGA-Verilog] Upgraded testbench generator to support memory bank using flatten BL/WLs
2021-09-25 17:49:15 -07:00
386812777c
[FPGA-Bitstream] Upgraded bitstream writer to support flatten BL/WLs
2021-09-25 12:49:32 -07:00
1a2a2a6e63
[FPGA-Bitstream] Relax fabric bitstream address check
2021-09-25 12:03:33 -07:00
8b72447dad
[FPA-Bistream] Updating fabric bitstream writer to organize bitstream for flatten BL/WLs
2021-09-24 18:07:07 -07:00
a49e3fe57a
[FPGA-bitstream] Upgraded bitstream generator to support flatten BL/WLs for QL memory bank
2021-09-24 16:30:18 -07:00
2de4a460a8
[Engine] Rework the function that counts the number of configurable children for fabric key writer and bitstream generator
2021-09-24 15:15:32 -07:00
74ffc8578f
[Engine] Upgraded fabric generator to support flatten BL/WL bus for memory banks
2021-09-24 15:05:25 -07:00
be4c850d2d
[Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs
2021-09-24 12:03:35 -07:00
18257b3fa1
[Engine] Update BL/WL port addition for the top-level module in fabric generator
2021-09-24 11:07:58 -07:00
7e27c0caf3
[Engine] Upgrading top-module fabric generation to support QL memory bank with flatten BL/WLs
2021-09-23 16:16:39 -07:00
8c281a22b0
[Engine] Add check codes to validate circuit models for BL/WL protocols
2021-09-23 14:39:16 -07:00
962acda810
[Engine] Bug fix in fabric key generation when computing configurable children
2021-09-22 11:09:46 -07:00
ad432e4d95
[Engine] Bug fix in finding the start index of BL/WL for each column/row;
2021-09-22 10:20:40 -07:00
b0a471bdc9
[Engine] Bug fix in outputting fabric key with coordinates
2021-09-21 15:55:11 -07:00
7688c0570f
[Engine] Support coordinate definition in fabric key file format; Now QL memory bank can accept fabric key
2021-09-21 15:08:08 -07:00
c84c0d4a3f
[FPGA-Verilog] Upgrade fpga-verilog to support decoders with WLR
2021-09-20 17:07:26 -07:00
36a4da863c
[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
2021-09-20 16:05:36 -07:00
2e45a6143b
[Engine] Fix a critical bug which causes flatten memory tests failed
2021-09-15 15:11:58 -07:00
f2aa31ddb1
[FPGA-Bitstream] Fix the bug which causes bitstream wrong for QL memory bank
2021-09-15 13:45:30 -07:00
061952b7fa
[Engine] Bug fix in computing local WLs for GRID/CB/SB
2021-09-15 11:51:00 -07:00
26b1e48723
[Engine] Merge BL/WLs in the Grid/CB/SB modules
2021-09-15 11:27:55 -07:00
4af6413c97
[Engine] Fixed a critical bug on WL arrangement; Previously we always consider squart of a local tile. Now we apply global optimization where the number of WLs are determined by the max. number of BLs per column
2021-09-10 17:03:44 -07:00
ba1e277dc9
[Engine] Fix a few bugs in the BL/WL arrangement and now bitstream generator is working fine
2021-09-10 15:05:46 -07:00
35c7b09888
[Engine] Bug fix for mistakes in calculating number of BLs/WLs for QL memory bank
2021-09-09 15:23:29 -07:00
b787c4e100
[Engine] Register QL memory bank as a legal protocol
2021-09-09 15:06:51 -07:00
1aac3197eb
[FPGA-Verilog] Upgrade testbench generator to support QL memory bank
2021-09-05 21:38:00 -07:00
6f09f5f7ad
[FPGA-Bitstream] Upgrade bitstream generator to support QL memory bank
2021-09-05 21:25:58 -07:00
1085e468e2
[Engine] Move most utilized functions for memory bank configuration protocol to a separated source file
2021-09-05 20:45:56 -07:00
475ce2c6d9
[Engine] Upgrade fabric generator in support QL memory bank connections
2021-09-05 17:49:01 -07:00
ed80d6b3f4
[Engine] Place QL memory bank source codes in a separated source file so that integration to OpenFPGA open-source version is easier
2021-09-05 13:23:38 -07:00
cf2e479d18
[Engine] Refactor the TopModuleNumConfigBits data structure
2021-09-05 12:01:38 -07:00
f75456e304
[Engine] Update BL/WL estimation function for QL memory bank protocol
2021-09-05 11:53:33 -07:00
5759f5f35b
[Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder
2021-09-03 17:55:23 -07:00
e9d29e27e5
[Tool] Bug fix
2021-07-02 15:32:30 -06:00
6e6c3e9fa4
[Tool] Patch the critical bug in the use of signal polarity in pin constraints
2021-07-02 15:26:21 -06:00
9074bffa68
[Tool] Support customized default value in pin constraint file
2021-07-01 23:43:19 -06:00
d0e4f8521f
[Tool] Bug fix on the reset stimuli
2021-07-01 19:58:54 -06:00
b5df1f9aeb
[Tool] Bug fix for redundant endif in netlists
2021-06-29 17:02:16 -06:00
b83eef47b4
[Tool] Bug fix for testbench generation without self checking codes
2021-06-29 16:27:29 -06:00
6a260cadbf
[Tool] Remove option ``--no_self_checking`` option but use the existing option ``--reference_benchmark_path`` to achieve the same purpose
2021-06-29 15:42:23 -06:00
7ac7de789e
[Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes
2021-06-29 15:26:40 -06:00
77dddaeb39
[Tool] Remove the preprocessing flags ``FORMAL_SIMULATION`` and ``FORMAL_VERIFICAITON`` because now ``write_testbench`` command can be called many times to generate different versions
2021-06-29 14:26:33 -06:00
a3208b332b
[Tool] Use 'force' in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL
2021-06-29 11:50:53 -06:00
dfe1db996a
[Tool] Remove the hardcoded factor when computing simulation timing; There should be no hidden parameters impacting simulation time
2021-06-29 09:56:04 -06:00
87446a14c3
[Tool] Bug fix for the option ``--embed_bitstream none``
2021-06-27 19:45:06 -06:00
991062e9bf
[Tool] Bug fix
2021-06-25 15:22:42 -06:00
90163fab6c
[Tool] Replace option '--support_icarus_simulator' with a new one '--preload_bitstream <string>'
2021-06-25 15:06:07 -06:00
2bb514c51a
[Tool] Support time unit in writing simulation information file
2021-06-25 10:33:29 -06:00
bcc16d732c
[Tool] Add new option 'testbench_type' so that simulation task can write different information for different testbenches
2021-06-25 10:10:16 -06:00
67dec810eb
[Tool] Remove icarus simulator flag; Reduce the file size of preconfigured fabric wrapper by only output the necessary force/deposit HDL codes
2021-06-24 17:27:32 -06:00
549657e1fb
[Tool] Remove out-of-date flag: INITIAL_SIMULATION from code base
2021-06-24 17:13:36 -06:00
5364d8104f
[Tool] Add signal_init option to preconfigured fabric wrapper writer
2021-06-24 17:07:41 -06:00
21d1519658
[Tool] Remove signal initialization flag; Now the HDL codes will not be outputted unless specified in the option
2021-06-24 16:56:28 -06:00
ce3c80f499
Merge branch 'master' into dev
2021-06-23 09:15:03 -06:00
cbbf601edc
[Tool] Fix a compiler warning due to uninitialized data structure
2021-06-18 16:20:13 -06:00
fed975c52a
[Tool] Add postfix removal support in write_io_mapping command
2021-06-18 16:13:50 -06:00
d9d57aad42
[Tool] Added default net type options to verilog testbench generator command
2021-06-14 11:37:49 -06:00
7ade48343c
[Tool] Deprecate command 'write_verilog_testbench'
2021-06-09 17:06:01 -06:00
2299ce3157
[Tool] Preconfigured testbench writer now supports icarus simulator
2021-06-09 13:49:25 -06:00
3bc8e760db
[Tool] Add '--fabric_netlist' option to 'write_preconfigured_testbench' command
2021-06-09 11:14:45 -06:00
89fb672631
[Tool] Fine-tune the options of 'write_simulation_task_info' to be straightforward to use
2021-06-09 10:49:00 -06:00
97396eda2b
[Tool] Add a new command 'write_simulation_task_info'
2021-06-08 22:10:02 -06:00
d2275b971d
[Tool] Add a new command 'write_preconfigured_testbench'
2021-06-08 21:53:51 -06:00
85679c0fe2
[Tool] Bug fix in the top testbench switch due to fast configuration
2021-06-08 21:32:26 -06:00
8db19c7af9
[Tool] Add a new command 'write_preconfigured_fabric_wrapper'
2021-06-08 21:28:16 -06:00
5075c68418
[Tool] Remove duplicated codes on fast configuration
2021-06-08 20:58:04 -06:00
4aef9d5c96
[Tool] Remove redundant codes
2021-06-07 21:54:01 -06:00
366dcff75d
[Tool] Now 'write_full_testbench' supports flatten(vanilla) configuration protocol
2021-06-07 21:49:31 -06:00
9808b61b36
[Tool] Bug fix on the unfit vector size of bit index register in Verilog testbench in some cases
2021-06-07 20:06:39 -06:00
ba75c18378
[Tool] Now 'write_full_testbench' supports memory bank configuration protocol
2021-06-07 17:40:07 -06:00
1a5902ca74
[Tool] Bug fix in finding pruned bitstream for frame-based protocol when fast configuration is enabled
2021-06-07 14:32:56 -06:00
af298de121
[Tool] Patch bugs in the full testbench writing using external bitstream file for frame-based configuration protocol
2021-06-07 13:53:32 -06:00
d644b8f22d
[Tool] Support external bitstream file when generating full testbench for frame-based decoder
2021-06-07 11:55:11 -06:00
618b04568f
[Tool] Remove unnecessary new line in bitstream file
2021-06-04 20:07:42 -06:00
cf7addb1a6
[Tool] Add heads to bitstream plain text file
2021-06-04 19:48:48 -06:00
70fb3a85dc
[Tool] Patch fast configuration in bitstream writing
2021-06-04 17:23:10 -06:00
d98be9f87b
[Tool] Remove icarus requirement on vcd writing in Verilog testbenches; Since vcd writing commands are standard Verilog
2021-06-04 16:45:00 -06:00
6e69c2d70a
[Tool] Patch fast configuration in full Verilog testbench generator
2021-06-04 16:34:55 -06:00
061f832429
[Tool] Enable fast configuration when writing fabric bitstream
2021-06-04 16:23:40 -06:00
81048d3698
[Tool] Add option '--fast_configuration' to 'write_full_testbench' command
2021-06-04 11:26:39 -06:00
98308133c1
[Tool] Add configuration skip capability to top testbench which loads external bitstream file
2021-06-04 11:24:05 -06:00
adb18d28b8
[Tool] Remove unused arguments
2021-06-04 10:37:28 -06:00
67485269d3
Merge branch 'master' into testbench_external_bitstream
2021-06-03 15:46:25 -06:00
ae6a46cd60
[Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique
2021-06-03 15:41:11 -06:00
1fd399736d
[Tool] Patch FPGA-SDC to consider time unit in global port timing constraints
2021-05-27 10:26:20 -06:00
c4ecc9ee7c
[Tool] Patch data type of report bitstream distribution command-line option
2021-05-07 11:44:01 -06:00
db9bb9124e
[Tool] Add report bitstream distribution command to openfpga shell
2021-05-07 11:41:25 -06:00
8728fd9561
[Tool] Typo fix to resolve clang errors
2021-04-27 15:06:07 -06:00
c5d36757c6
[Tool] Fix typo in io mapping writing
2021-04-27 14:39:57 -06:00
43c1e052ef
[Tool] Add a writer to output I/O mapping information to XML files
2021-04-27 14:30:16 -06:00
148da80869
[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes
2021-04-24 14:53:29 -06:00
0709e5bb81
[Tool] Fixed a bug in the routing trace finder for direct connections inside repacker
2021-04-24 13:27:44 -06:00
56948244bc
[Tool] Patch a critical bug in pb pin fixup
2021-04-22 16:19:54 -06:00
96ce6b545f
[Tool] Patch repack to consider design constraints for pins that are not equivalent
2021-04-21 13:53:08 -06:00
0aec30bac6
[Tool] Update FPGA core engine to support mux default path overloading through bitstream setting file
2021-04-19 15:53:33 -06:00
0b49c22682
[Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks
2021-04-18 16:11:11 -06:00
6550ea3dfa
[Tool] Rework pin constarint API to avoid expose raw data to judge for developers
2021-04-18 12:02:49 -06:00
6e9b24f9bf
[Tool] Patch the invalid pin constraint net name
2021-04-17 19:56:30 -06:00
253422e7b7
[Tool] Bugfix due to refactoring
2021-04-17 19:27:03 -06:00
02ca51d84b
[Tool] Reorganize functions in full testbench generator to avoid big-chunk codes
2021-04-17 17:45:50 -06:00
d95a1e2776
[Tool] Encapulate search function in PinConstraint data structure
2021-04-17 17:31:55 -06:00
da619fabe7
[Tool] FPGA-Verilog testbench generator accepts pin constraints in full testbench
2021-04-17 17:19:34 -06:00
6e1b58f8a6
[Tool] Update FPGA-Verilog testbench generator to accept pin constraints to non-clock global ports
2021-04-17 15:05:22 -06:00
7c6e000be8
[Tool] bug fix
2021-04-10 15:36:02 -06:00
03b68a1fdd
[Tool] Reworked fabric bitstream XML writer to consider multiple configuration regions
2021-04-10 15:25:39 -06:00
934918d9c0
[Tool] Reworked fabric bitstream output file in plain text format; Support multiple regions
2021-04-10 15:06:53 -06:00
4b8f5f294a
[Tool] Capsulate fabric bitstream organization for configuration chain
2021-04-10 14:28:31 -06:00
afa0e751da
[Tool] Use alias for complex bitstream data types
2021-04-10 14:12:02 -06:00
902c4cf9e9
Merge branch 'master' into dev
2021-03-18 15:14:14 -06:00
3ef292bdbb
Merge branch 'netlist_name_patch' of https://github.com/LNIS-Projects/OpenFPGA into netlist_name_patch
2021-03-17 20:28:40 -06:00
fa11410425
[Tool] Remove exceptions on outputing verilog port with lsb=0
2021-03-17 20:27:08 -06:00
62a846197b
Merge branch 'master' into dev
2021-03-15 10:06:34 -06:00
87006e1374
Merge branch 'master' into netlist_name_patch
2021-03-15 10:06:24 -06:00
024aa5cbe4
Merge branch 'master' into dev
2021-03-15 09:13:18 -06:00
d2fbda4070
Merge branch 'master' into netlist_name_patch
2021-03-15 09:13:04 -06:00
b080bcf018
Merge branch 'master' into ganesh_dev
2021-03-15 09:12:50 -06:00
02967f2870
Added writing rr graph node indices to GSB dump.
...
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-03-15 09:28:38 +01:00
c8d41b4e69
[Tool] Change routing module port naming to include architecture port names
2021-03-14 19:35:49 -06:00
956b9aca01
[Tool] Trim dead codes in port naming function
2021-03-13 20:23:08 -07:00
2c5634ee76
[Tool] Change pin naming of grid modules to be related to architecture port names
2021-03-13 20:05:18 -07:00
07257d0ff0
[Tool] Patch wrong paths in FPGA-SDC
2021-03-13 10:58:03 -07:00
d877a02534
[Tool] Patch the extended bitstream setting support on mode-select bits
2021-03-10 21:28:09 -07:00
85640a7403
[Tool] Extend bitstream setting to support mode bits overload from eblif file
2021-03-10 20:45:48 -07:00
e34380a654
Merge branch 'master' into default_net_type
2021-03-01 08:38:58 -07:00
521e1850c8
[Tool] Correct syntax errors for timing definition in verilog for iverilog 10.1
2021-02-28 17:04:27 -07:00
73461971d2
[Tool] Bug fix for printing single-bit ports in Verilog netlists
2021-02-28 16:12:57 -07:00
15e26a5602
[Tool] Support default_net_type Verilog syntex in fabric generator
2021-02-28 11:57:40 -07:00
df7b436ac7
[Tool] Patch repacker to support duplicated nets due to adder nets
2021-02-23 19:01:18 -07:00
e6091fb3ff
[Tool] Now throw fatal error on mismatch in configurable regions between fabric key and architecture definition
2021-02-18 21:56:30 -07:00
a5b8b2a64a
[Tool] Use dedicated function to identify wire LUT created by repacker
2021-02-18 19:37:44 -07:00
aae03482f5
[Tool] Bug fix for wire LUT identification by repacker. Create a dedicated function to identify these LUTs and store the results in shared database
2021-02-18 19:37:17 -07:00
61012897cd
[Tool] Bug fix for truth table creation for wired LUT created by repacking algorithm
2021-02-17 15:31:20 -07:00
af4cc117fb
[Tool] bug fix in spypad lut
2021-02-09 22:53:18 -07:00
6a0f4f354f
[Tool] Support superLUT circuit model in core engine
2021-02-09 20:23:05 -07:00
0c409b5bcc
[Tool] Add bitstream annotation support
2021-02-01 20:49:36 -07:00
f102e84497
[Tool] Add bitstream setting file to openfpga library
2021-02-01 17:43:46 -07:00
4b77a3a574
[Tool] Now activity file is not a manadatory input of openfpga tools
2021-01-29 11:33:40 -07:00
d9fda31a9f
[Tool] Add --version to openfpga shell option and a command to openfpga shell
2021-01-27 16:03:46 -07:00
fd0e73a9bb
[Tool] Enhance return code for openfpga shell
2021-01-24 14:48:27 -07:00
8cac3291cb
[Tool] Add batch mode to openfpga shell execution
2021-01-24 14:33:58 -07:00
d502410b40
Merge pull request #179 from lnis-uofu/unused_gpout_patch
...
Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches
2021-01-23 18:27:54 -07:00
4cc8b08a6c
[Tool] Add openfpga version display
2021-01-23 16:38:00 -07:00
d2defebee9
[Tool] Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches
2021-01-22 16:42:13 -07:00
3f80a26172
[Tool] Bug fix for combinational benchmarks in pre-config testbench generation
2021-01-19 18:22:50 -07:00
75b99b78e9
[Tool] Now testbench generator consider pin constraints in generating clock sources for benchmarks
2021-01-19 17:38:51 -07:00
da200658c1
[Tool] Now autocheck top testbench consider pin constraints to generate operating clock sources for benchmarks
2021-01-19 17:29:59 -07:00
0670c2de59
[Tool] Deploy pin constraints to preconfig Verilog module generation
2021-01-19 16:56:30 -07:00
8c311b8282
[Tool] Bug fix in repacker for considering design constraints
2021-01-17 12:26:14 -07:00
2efe513122
[Tool] Now repack consider design constraints; test pending
2021-01-16 21:57:17 -07:00
bb8e7e25c2
[Tool] Start deploying design constraints in repack engine
2021-01-16 21:27:12 -07:00
fa67517349
[Tool] Add repack design constraints to openfpga command 'repack'
2021-01-16 18:49:34 -07:00
ad7a54db1b
[Tool] Add repack dc library to compilation
2021-01-16 17:20:59 -07:00
87b2c1f3b8
[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
2021-01-15 12:01:53 -07:00
852f5bb72e
[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
2021-01-14 15:38:24 -07:00
9cc9e45b4b
[Tool] Apply a dirty fix to Verilog testbench generator so that multi-clock testbench can be generated
2021-01-13 15:13:19 -07:00
c0da6b900a
[Tool] Bug fix in creating multi-bit clock port connections
2021-01-12 18:38:00 -07:00
65b2fe3ab7
[Tool] Bug fix in the global tile connection by considering all the subtiles
2021-01-10 11:52:38 -07:00
9a441fa5cc
[Tool] Upgrade openfpga to support extended global tile port definition
2021-01-09 18:47:12 -07:00
cde26597ed
[Tool] Bug fix in scan chain builder calling
2021-01-04 18:45:47 -07:00
804b721a19
[Tool] Bug fix in the configuration chain connection builder
2021-01-04 17:41:29 -07:00
bfd305b5a5
[Tool] Patch the bug in finding data output ports for CCFF
2021-01-04 17:22:30 -07:00
cc91a0aebd
[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
2021-01-04 17:14:26 -07:00
d11a3d9fef
[Tool] Avoid outputting signal initialization codes because they are bulky
2020-12-06 14:29:16 -07:00
cb2bd2e31c
[Tool] Remove register ports for mini local encoders (1-bit data out)
2020-12-06 14:21:54 -07:00
6bdfcb0147
[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
2020-12-05 12:44:09 -07:00
6f18688f0e
[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
2020-12-05 10:53:01 -07:00
0da92ad888
[Tool] Split MUX Verilog netlist into two separated files: one contains only primitives while the other contains the top-level modules
2020-12-04 22:16:51 -07:00
5be9e9b736
[Tool] Adapted tools to support I/O in center grid
2020-12-04 18:50:13 -07:00
73aaa261d8
[Tool] Relax the IO restriction in pb_pin post-routing packing fix-up
2020-12-04 17:55:25 -07:00
4aa6264b1c
[Tool] Rework simulation time period to be sync with actual stimuli
2020-12-02 22:58:13 -07:00
b661c39b04
[Tool] Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches
2020-12-02 19:36:36 -07:00
3a708cff21
[Tool] Bug fix to enable nature fracturable LUT design
2020-11-25 23:01:18 -07:00
c82f01b3ab
[Tool] Use conditional operator in signal initialization to eliminate all the warning messages
2020-11-23 15:50:23 -07:00
e644545f21
[Doc] Remove signal initialization for select ports of MUXes and Pass-gates; Use urandom to generate just-fit random vectors
2020-11-23 15:02:06 -07:00
3b2a4c5387
[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists
2020-11-22 20:25:03 -07:00
57a24570f5
[Tool] Move icarus and signal initialization options to testbench generator
2020-11-22 16:01:31 -07:00
3f91b8433e
[Tool] Change the i/o numbering to the clockwise sequence
2020-11-13 15:00:25 -07:00
088198c861
[Tool] enhance error checking in fabric key parser
2020-11-13 10:56:00 -07:00
372fb261fd
[Tool] Extend the support on global tile port for I/O tiles
2020-11-11 15:09:40 -07:00
e627b6dd5d
[Tool] Enhance port attribute checks in tile annotation data structure
2020-11-11 13:41:05 -07:00
9cbc374b33
[Tool] Add check codes for tile annotation
2020-11-11 12:03:13 -07:00
81e56d45d6
[Tool] Update FPGA-SDC to use the new data structure for global ports
2020-11-10 21:17:17 -07:00
c61ec5a8b8
[Tool] Bug fix for defining global ports from tiles
2020-11-10 20:31:14 -07:00
dcb50e4f19
[Tool] Use use standard data structure to store global port information
2020-11-10 19:07:28 -07:00
cbb1545ee3
[Tool] Add connection builder for tile global ports to top-level module
2020-11-10 16:59:00 -07:00
5fe9c27600
[Tool] Remove redundant assertation
2020-11-09 09:42:39 -07:00
ba0120bd76
[Tool] Remove the limitation on requiring Qb ports for CCFF
2020-11-06 11:10:04 -07:00
9b0617ffe6
[Tool] Bug fix for mappable I/O support
2020-11-04 20:45:51 -07:00
37c10f0cb5
[Tool] Add mappable I/O support and enhance I/O support
2020-11-04 20:21:49 -07:00
4a2874b2bc
[Tool] Refactor the codes for walking through io blocks
2020-11-03 13:21:50 -07:00
1e47203c7c
[Tool] Auto-generated gate Verilog netlist should not contain any signal initalization
2020-11-02 18:35:26 -07:00
e4d974c5c8
[Tool] Split io location mapping builder from fabric builder
2020-11-02 18:27:34 -07:00
1fd899ecee
[Tool] Relex logic block checking codes to skip zero-capacity nodes
2020-11-02 16:57:19 -07:00
6b25cf720d
[Tool] Comment on the memory efficiency on fabric bitstream address storage
2020-10-30 22:09:48 -06:00
b78f8bec16
[Tool] Bug fixed for multi-region configuration frame
2020-10-30 21:19:20 -06:00
5bcd559851
[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
2020-10-30 17:29:04 -06:00
0d77916041
[Tool] Support multi-region frame-based configuration protocol
2020-10-30 10:43:11 -06:00
8ef6ae32fb
[Tool] Bug fix for bitstream estimator due to the current special status of frame-based protocol
2020-10-29 17:35:55 -06:00
987eccf586
[Tool] Bug fix in multi-region memory bank; Basic test passed
2020-10-29 16:26:45 -06:00
448e88645a
[Tool] Support multiple memory banks in top-level module
2020-10-29 12:42:03 -06:00
bd49ea95d4
[Tool] Add function to comput configuration bits by region
2020-10-28 12:37:09 -06:00
446f982410
[Tool] Add warning when number of regions defined in fabric key is different than architecture
2020-10-28 11:43:05 -06:00
1ef0898f41
[Tool] Now users can specify a different fabric netlist when generating Verilog testbench
2020-10-12 12:31:51 -06:00
721bcce373
[Tool] Change analysis SDC file name to track netlist name
2020-10-10 17:43:35 -06:00
e0d7bcfa11
[Tool] Bug fix for region-based fabric bitstream using memory bank and frame-based protocols
2020-09-29 12:49:32 -06:00
e988e35f81
[Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches
2020-09-29 12:22:10 -06:00
180d72f3e5
[Tool] Add regions to fabric bitstream
2020-09-28 21:04:08 -06:00
e179a58b15
[OpenFPGA Tool] Bug fix for long runtime
2020-09-28 20:42:18 -06:00
47f3c79927
[OpenFPGA Tool] Bug fix in module manager due to configurable regions
2020-09-28 19:08:19 -06:00
f93d46a870
[OpenFPGA Tool] Add multiple configuration chain support in top module builder
2020-09-28 19:03:19 -06:00
552dddffd0
[OpenFPGA Tool] Support configurable regions in module manager
2020-09-28 18:13:07 -06:00
052b8b71c7
[OpenFPGA Tool] Bug fix in the XML parser for fabric regions
2020-09-27 20:54:58 -06:00
154f23b108
[OpenFPGA Tool] Add self-testing Verilog codes for configuration done signals in full testbenches
2020-09-26 11:54:06 -06:00
1b4e449179
[OpenFPGA Tool] Critical bug fix for Verilog testbenches for memory bank and frame-based configuration protocol
2020-09-25 21:05:20 -06:00
6bea712db0
[OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name
2020-09-25 14:54:51 -06:00
8468f25b23
[OpenFPGA Tool] Bug fix in the smart fast configuration strategy
2020-09-24 16:31:55 -06:00
46b12611a9
[OpenFPGA Tool] Bug fix for smart fast configuration
2020-09-23 22:04:07 -06:00
154c9045f6
[OpoenFPGA Tool] Bug fix for smart fast configuration
2020-09-23 21:38:42 -06:00
c2c37d7555
[OpenFPGA Tool] Add more print-out for smart fast configuration
2020-09-23 21:34:23 -06:00
a3abf81afe
[OpenFPGA Tool] Support on set signals and smart selection between reset and set signal for fast configuration
2020-09-23 21:25:06 -06:00
064678fe32
[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
2020-09-23 20:27:52 -06:00
ad881ea4dc
[OpenFPGA Tool] Bug fix for Verilog testbench using frame-based /memory bank
2020-09-23 18:59:25 -06:00
9adeb550dc
[OpenFPGA Tool] Bug fix in fabric builder
2020-09-23 18:28:00 -06:00
6480b06a2d
[OpenFPGA tool] Remove out-of-data test blif, architecture and scripts
2020-09-23 11:01:53 -06:00
26f1a5d9ec
[OpenFPGA Tool] Bug fix for repacking no local routing architecture
2020-09-21 22:22:03 -06:00
c6ac02d210
[FPGA-SPICE] Add VDD/VSS ports to SPICE subckt instanciation
2020-09-20 15:21:33 -06:00
544c44fe46
[FPGA-SPICE] Add VDD and VSS port to module definition
2020-09-20 14:58:15 -06:00
460fef5807
[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions
2020-09-20 12:58:55 -06:00
222bc86cbf
[FPGA-SPICE] Add auxiliary SPICE netlist writer
2020-09-20 12:53:28 -06:00
06c0073a3e
[FPGA-SPICE] Add SPICE writer for fpga top module
2020-09-20 12:43:48 -06:00
1dfb3e06cc
[FPGA-SPICE] add SPICE writer for logic blocks
2020-09-20 12:38:24 -06:00
5e78e91fdf
[FPGA-SPICE] Add SPICE writer for routing blocks
2020-09-20 12:27:48 -06:00
0f25b52907
[FPGA-Verilog] code format fix
2020-09-20 12:18:22 -06:00
2fae311c8e
[FPGA-SPICE] Add SPICE writer for memories
2020-09-20 12:14:34 -06:00
f284f6f8d0
[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
2020-09-20 12:03:10 -06:00
6801d260e9
[FPGA-SPICE] Add SPICE writer for LUT
2020-09-20 11:58:11 -06:00
0f9fce92b2
[FPGA-SPICE] Add SPICE writer for routing multiplexers
2020-09-20 11:49:02 -06:00
c7e3d97d1b
[FPGA-SPICE] Add supply voltage generator
2020-09-20 11:19:06 -06:00
15df9b3893
[FPGA-SPICE] Add SPICE subcircuit writer
2020-09-19 23:01:44 -06:00
82e137cbe4
[FPGA-SPICE] Add wire module SPICE writer
2020-09-19 19:31:16 -06:00
1b2762386c
[FPGA-SPICE] Bug fix for essential gate netlist writing
2020-09-19 16:52:30 -06:00
26a0a769ea
[FPGA-SPICE] Split essential gate SPICE netlists into separated files
2020-09-19 16:45:26 -06:00
e102e30d19
[FPGA-SPICE] Add support for AND/OR logic gate
2020-09-19 16:20:21 -06:00
482d90018f
[FPGA-SPICE] Create generic PMOS/NMOS instanciation function
2020-09-19 15:33:28 -06:00
3262ceb276
[FPGA-SPICE] Bug fix for pass gate transistor sizing
2020-09-19 15:24:40 -06:00
aa078f079c
[FPGA-SPICE] Restructured SPICE netlist writers for atom circuits to avoid large cpp files
2020-09-19 15:20:19 -06:00
f5dadca884
[FPGA-SPICE] Optimize the print-out of SPICE ports
2020-09-19 15:07:48 -06:00
51d423e4db
[FPGA-SPICE] Add pass-gate SPICE netlist writer
2020-09-19 14:59:00 -06:00
9cfb2f52ef
[OpenFPGA code] bug fix for fully equivalent outputs of pb_type
2020-09-16 19:26:46 -06:00
fc6bfdc7a2
[OpenFPGA Code] Patch syntax compatibility for older gcc
2020-09-14 18:55:21 -06:00
04070fd4ca
[Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker
2020-09-02 22:16:10 -06:00
3eea12ceae
added a new XML syntax: initial offset for physical mode pin mapping
2020-08-19 14:43:44 -06:00
f631245b2b
bug fix and enriched debugging info print out
2020-08-19 13:41:04 -06:00
79b6ff3cb0
relax checking for device annotation as we support multi-port during physical mode pin mapping
2020-08-19 12:44:51 -06:00
2712c354a9
now physical pb_port binding support multiple ports
2020-08-18 12:38:56 -06:00
5d83abb2cf
bug fix in read architecture bitstream and regression tests
2020-07-27 19:37:05 -06:00
9a7364c6e6
bug fix in fabric bitstream XML syntax
2020-07-27 19:22:36 -06:00
35af0dd676
streamline fabric bitstream file format
2020-07-27 16:34:43 -06:00
8dd26094b8
add root node to fabric bitstream XML file format
2020-07-27 15:31:08 -06:00
6592db3dfe
bug fix in calling the wrong function of write_fabric_bitstream
2020-07-27 14:32:58 -06:00
d68e77f322
Split the writer of build_fabric_bitstream to a separated command so that users will output multiple files in different formats
2020-07-27 14:16:33 -06:00
e09eddab43
add width syntex to the fabric bitstream file format
2020-07-27 13:54:23 -06:00
80e982fb39
minor file format fix in fabric bitstream XML
2020-07-26 21:35:48 -06:00
b3ad04fd1e
minor file format fix in fabric bitstream XML
2020-07-26 21:33:47 -06:00
861e346830
minor bug fix in fabric bitstream XML writer
2020-07-26 21:31:08 -06:00
5fb7d9fbdb
bug fix in fabric bitstream file format writer
2020-07-26 21:28:45 -06:00
92d2d2d849
add fabric bitstream XML writer
2020-07-26 21:00:57 -06:00
a3d22c56e3
bug fix in FPGA-SPICE
2020-07-24 19:51:32 -06:00
fd3e947c6d
update FPGA_SPICE to support max width for transistors and multi-bin
2020-07-24 17:52:31 -06:00
73e2b857a3
add buffer support to FPGA-SPICE
2020-07-24 15:54:18 -06:00
2603836111
split logical tile netlists to keep good Verilog hierarchy
2020-07-24 12:53:21 -06:00
be5966475e
formulate file name, module name and instance name to be consistent
2020-07-24 12:23:27 -06:00
22159531c5
bug fix in power gating support of FPGA-Verilog
2020-07-22 20:21:38 -06:00
a4a38f8156
support multi-bit power gate ports in FPGA-SPICE
2020-07-22 20:04:39 -06:00
f573fa3ee0
move check codes on power gate ports to libarchopenfpga
...
Try to report errors to users as early as possible
2020-07-22 18:47:12 -06:00
97cca72590
add spice support on power gated inverters
2020-07-22 18:21:11 -06:00
b5fd6aa859
add inverter subckt writer to FPGA-SPICE
2020-07-17 13:01:08 -06:00
eb070694b5
fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture
2020-07-15 17:52:41 -06:00
66a50742fc
use configuration chain in the k4k4 test case to speed up CI
2020-07-15 11:56:11 -06:00
3f14fe62c7
add fast configuration support for configuration chain protocol
2020-07-15 11:44:23 -06:00
1b55dfb441
hotfix on treating the dangling ports in pb_graph for analysis SDC generator
2020-07-09 23:28:42 -06:00
62fd0947f5
using a unified string to replace multi net names to save memory of bitstream database
2020-07-08 16:28:20 -06:00
66e5e141a1
improve fabric key loader to reduce runtime
2020-07-07 10:19:34 -06:00
824b56f14c
fabric key can now accept instance name only; decoders are no longer part of the key
2020-07-06 16:42:33 -06:00
462fc0d04e
add spice transistor wrapper writer
2020-07-05 14:50:29 -06:00
b38ee0e8be
add spice writer functions
2020-07-05 13:58:05 -06:00
81171a8f97
start transplanting FPGA-SPICE
2020-07-05 12:10:12 -06:00
1ad6e8292a
move constants from verilog domain to common so that FPGA-SPICE can share
2020-07-05 11:39:46 -06:00
7c2a0a6ad2
streamline fabric verilog options
2020-07-05 11:28:14 -06:00
83e26adf90
add module usage types for future FPGA-SPICE development
2020-07-04 22:33:54 -06:00
4f8260a7ba
remove obselete codes and update regression tests
2020-07-04 17:31:34 -06:00
033c92c365
precisely reserve memory for child blocks in bitstream manager
2020-07-03 22:47:21 -06:00
46f038c829
bug fix in grid config block allocation
2020-07-03 20:46:04 -06:00
f040fc78a9
now reserve blocks in bitstream manager can accurately capture the size
2020-07-03 20:06:12 -06:00
8067a13346
bug fix for memory bank due to encoding bl/wl addresses in fabric bitstream
2020-07-03 15:56:20 -06:00
2a9377b3f4
use encoded address in storage of fabric bitstream to save memory
2020-07-03 15:12:29 -06:00
1f38e17111
bug fix for naming conflicts in mux local encoder and architecture decoders
2020-07-03 14:12:13 -06:00
70d9678578
reserve child block in bistream manager
2020-07-03 14:04:10 -06:00
2783fda344
use index range instead of vector for block bitstream
2020-07-03 11:42:38 -06:00
6ea857ae6c
use fast method to inquire number of bits and blocks in bitstream databases
2020-07-03 10:55:25 -06:00
7ca1a5bdc1
Fabric bitstream now allocates vectors in conditions for memory efficiency
2020-07-03 10:17:03 -06:00
8a45e48a1c
minor fix
2020-07-02 22:27:48 -06:00
246b4d5ac6
reserve block bits to save memory
2020-07-02 21:52:32 -06:00
dee4be96af
reserve all the input/output net storage in bitstream manager
2020-07-02 19:17:34 -06:00
f97e3bfba6
add timer to openfpga shell
2020-07-02 18:02:33 -06:00
81c9fcb7c0
bug fix when optimizing the fabric bitstream data structure
2020-07-02 16:41:32 -06:00
adee87569d
enable fast bitstream building by creating a frame view of fabric
2020-07-02 16:25:36 -06:00
9608cefa86
remove id vector in fabric bitstream database and replace with more memory efficient implementation
2020-07-02 16:08:50 -06:00
9f19c36a89
use char in fabric bitstream to save memory footprint
2020-07-02 15:56:50 -06:00
405824081b
reserve configuration blocks and bits in bitstream manager builder to be memory efficient
2020-07-02 15:28:52 -06:00
b85af57971
optimizing fabric bitsteream memory footprint
2020-07-02 12:39:18 -06:00
ac22ba28e4
add config protocol type information to simulation ini file
2020-07-02 12:26:59 -06:00
81ecfa3197
add comments to clarify how to select CB ports when connecting to SBs at the top level
2020-07-01 14:44:40 -06:00
0a3c746fb1
now split CB module bus ports into lower/upper parts
2020-07-01 14:37:13 -06:00
cb2baed257
bug fix in simulation ini GPIO width
2020-07-01 13:39:12 -06:00
b74dde919d
add additional information in the simulation ini file for UVM
2020-07-01 13:07:39 -06:00
e688ca1388
update fabric bitstream writer to support various configuration protocols
2020-07-01 11:54:28 -06:00
1015880d0e
use easy-to-access net look up in switch block module builder
2020-06-30 18:15:41 -06:00
05187f8aa4
use typedef to short the module pin information
2020-06-30 18:07:22 -06:00
2e7684b746
adapt bus ports in connection block module builder
2020-06-30 17:50:53 -06:00
2ef083c49d
adapt SB module builder to use bus ports
2020-06-30 16:02:40 -06:00
f023652ac4
keep optimizing memory footprint of module manager by using net terminal storage
2020-06-30 14:18:05 -06:00
f49cabeeda
optimize memory efficiency for module net id storage
2020-06-30 11:33:06 -06:00
23bcad0678
use more robust net builder in inter tile connections
2020-06-30 10:49:17 -06:00
025d4a3599
use efficient net builder in top module connection builder
2020-06-29 23:28:26 -06:00
e7d5736269
add profile time to top module builder for better spot on runtime/memory overhead sources
2020-06-29 23:17:03 -06:00
57e6c84252
add reserve net sources and sinks to module manager
2020-06-29 22:49:11 -06:00
66746f69da
optimizing memory efficiency by reserving nets in module manager
2020-06-29 21:27:43 -06:00
e9937954f2
optimizing the constant writing in Verilog for single bits
2020-06-29 12:29:25 -06:00
9d32a5b81f
add alias name support for fabric key
2020-06-27 14:59:53 -06:00
ebf5636e7b
add verbose output to edge sorting for GSBs
2020-06-26 17:10:51 -06:00
aded675633
rename files in fpga bitstream library to be consistent with conventions
2020-06-21 13:06:39 -06:00
d526f08782
deploy bitstream reader in openfpga shell
2020-06-20 18:48:19 -06:00
675a59ecb8
Move fpga_bitstream to the libopenfpga library and add XML reader
2020-06-20 18:25:17 -06:00
5d79a3f69f
critical bug fixed when annotating the routing results.
...
Add previous node check. This is due to that some loops between SB/CBs may exist
when routing congestion is high, which leads to same nets appear in the inputs
of a routing multiplexer. Actually one of them is driven by the other as a downstream node
Using previous node check can identify which one to pick
2020-06-17 11:17:57 -06:00
4f7e8020a8
minor fix on the format of arch bitstream writer
2020-06-17 00:08:28 -06:00
b91c30191a
add input and output net echo in arch bitstream database
2020-06-17 00:04:55 -06:00
19c0b57df6
ignore invalid nets when decoding bitstream
2020-06-16 22:26:36 -06:00
9d0e002532
echo path in architecture bitstream database
2020-06-16 21:29:45 -06:00
559564c333
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
2020-06-12 17:31:14 -06:00
a5055e9d26
add support about loading external fabric key
2020-06-12 13:03:11 -06:00
9dbf536306
add shuffled configurable children support for top module
2020-06-12 11:16:53 -06:00
cf9c3b0f44
add write fabric to test cases
2020-06-12 10:50:23 -06:00
3499b4d3e7
add fabric key writer for top-level module
2020-06-12 10:41:34 -06:00
278acee216
bug fix for 'build_fabric' command
2020-06-11 23:59:24 -06:00
9167b288b6
add options for fabric key
2020-06-11 21:50:46 -06:00
8a4ec85c39
add configurable children-related methods to module manager
2020-06-11 21:44:25 -06:00
58807bfcb3
remove simulation settings from openfpga arch data structure
2020-06-11 19:31:16 -06:00
96b58dfdbb
use new simulation setting command in openfpga shell
2020-06-11 19:31:15 -06:00
4a2f6dfae2
add read/write simulation setting commands to openfpga shell
2020-06-11 19:31:15 -06:00
3c10af7f2b
bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm
2020-06-11 19:31:14 -06:00
8267dad8ef
add decoder support for Z signals
2020-06-11 19:31:14 -06:00
5368485bd6
keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
2020-06-11 19:31:14 -06:00
c85ccceac7
try bug fixing in memory bank configuration protocol
2020-06-11 19:31:14 -06:00
0bee70bee6
finish memory bank configuration protocol support.
2020-06-11 19:31:13 -06:00
e14c39e14c
update Verilog full testbench generation to support memory bank configuration protocol
2020-06-11 19:31:13 -06:00
51e1559352
add fabric bitstream support for memory bank configuration protocol
2020-06-11 19:31:13 -06:00
0e16ee1030
add configuration bus nets for memory bank decoders at top module
2020-06-11 19:31:13 -06:00
fa8dfc1fbd
add configuration protocol ports to top module for memory bank organization
2020-06-11 19:31:13 -06:00
ad7422359d
deploy compact constant values in Verilog codes
2020-06-11 19:31:13 -06:00
8ec8ac4118
bug fixed in flatten memory organization. Passed verification
2020-06-11 19:31:12 -06:00
b9aac3cbdf
updated fpga verilog testbench generation to support vanilla (standalone) configuration protocol
2020-06-11 19:31:12 -06:00
fbe05963e0
add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol)
2020-06-11 19:31:12 -06:00
tangxifan
Maciej Kurc
ganeshgore