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[OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name

This commit is contained in:
tangxifan 2020-09-25 14:54:51 -06:00
parent 019208ec0f
commit 6bea712db0
2 changed files with 27 additions and 19 deletions
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10
openfpga/src/fabric/build_essential_modules.cpp
View File

@ -256,7 +256,15 @@ void rename_primitive_module_port_names(ModuleManager& module_manager,
/* We only care about user-defined models */
if ( (true == circuit_lib.model_verilog_netlist(model).empty())
&& (true == circuit_lib.model_spice_netlist(model).empty()) ) {
continue;
/* Exception circuit models as primitive cells
* - Inverter, buffer, pass-gate logic, logic gate
* which should be renamed even when auto-generated
*/
if ( (CIRCUIT_MODEL_INVBUF != circuit_lib.model_type(model))
&& (CIRCUIT_MODEL_PASSGATE != circuit_lib.model_type(model))
&& (CIRCUIT_MODEL_GATE != circuit_lib.model_type(model)) ) {
continue;
}
}
/* Skip Routing channel wire models because they need a different name. Do it later */
if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) {

36
openfpga/src/fpga_verilog/verilog_essential_gates.cpp
View File

@ -43,7 +43,7 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp,
print_verilog_comment(fp, std::string("----- Verilog codes of a power-gated inverter -----"));
/* Create a sensitive list */
fp << "\treg " << circuit_lib.port_prefix(output_port) << "_reg;" << std::endl;
fp << "\treg " << circuit_lib.port_lib_name(output_port) << "_reg;" << std::endl;
fp << "\talways @(";
/* Power-gate port first*/
@ -52,10 +52,10 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp,
if (false == circuit_lib.port_is_config_enable(power_gate_port)) {
continue;
}
fp << circuit_lib.port_prefix(power_gate_port);
fp << circuit_lib.port_lib_name(power_gate_port);
fp << ", ";
}
fp << circuit_lib.port_prefix(input_port) << ") begin" << std::endl;
fp << circuit_lib.port_lib_name(input_port) << ") begin" << std::endl;
/* Dump the case of power-gated */
fp << "\t\tif (";
@ -79,14 +79,14 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp,
fp << "~";
}
fp << circuit_lib.port_prefix(power_gate_port) << "[" << power_gate_pin << "])";
fp << circuit_lib.port_lib_name(power_gate_port) << "[" << power_gate_pin << "])";
port_cnt++; /* Update port counter*/
}
}
fp << ") begin" << std::endl;
fp << "\t\t\tassign " << circuit_lib.port_prefix(output_port) << "_reg = ";
fp << "\t\t\tassign " << circuit_lib.port_lib_name(output_port) << "_reg = ";
/* Branch on the type of inverter/buffer:
* 1. If this is an inverter or an tapered(multi-stage) buffer with odd number of stages,
@ -101,12 +101,12 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp,
fp << "~";
}
fp << circuit_lib.port_prefix(input_port) << ";" << std::endl;
fp << circuit_lib.port_lib_name(input_port) << ";" << std::endl;
fp << "\t\tend else begin" << std::endl;
fp << "\t\t\tassign " << circuit_lib.port_prefix(output_port) << "_reg = 1'bz;" << std::endl;
fp << "\t\t\tassign " << circuit_lib.port_lib_name(output_port) << "_reg = 1'bz;" << std::endl;
fp << "\t\tend" << std::endl;
fp << "\tend" << std::endl;
fp << "\tassign " << circuit_lib.port_prefix(output_port) << " = " << circuit_lib.port_prefix(output_port) << "_reg;" << std::endl;
fp << "\tassign " << circuit_lib.port_lib_name(output_port) << " = " << circuit_lib.port_lib_name(output_port) << "_reg;" << std::endl;
}
/************************************************
@ -124,7 +124,7 @@ void print_verilog_invbuf_body(std::fstream& fp,
print_verilog_comment(fp, std::string("----- Verilog codes of a regular inverter -----"));
fp << "\tassign " << circuit_lib.port_prefix(output_port) << " = (" << circuit_lib.port_prefix(input_port) << " === 1'bz)? $random : ";
fp << "\tassign " << circuit_lib.port_lib_name(output_port) << " = (" << circuit_lib.port_lib_name(input_port) << " === 1'bz)? $random : ";
/* Branch on the type of inverter/buffer:
* 1. If this is an inverter or an tapered(multi-stage) buffer with odd number of stages,
@ -139,7 +139,7 @@ void print_verilog_invbuf_body(std::fstream& fp,
fp << "~";
}
fp << circuit_lib.port_prefix(input_port) << ";" << std::endl;
fp << circuit_lib.port_lib_name(input_port) << ";" << std::endl;
}
/************************************************
@ -264,8 +264,8 @@ void print_verilog_passgate_module(const ModuleManager& module_manager,
/* Dump logics: we propagate input to the output when the gate is '1'
* the input is blocked from output when the gate is '0'
*/
fp << "\tassign " << circuit_lib.port_prefix(output_ports[0]) << " = ";
fp << circuit_lib.port_prefix(input_ports[1]) << " ? " << circuit_lib.port_prefix(input_ports[0]);
fp << "\tassign " << circuit_lib.port_lib_name(output_ports[0]) << " = ";
fp << circuit_lib.port_lib_name(input_ports[1]) << " ? " << circuit_lib.port_lib_name(input_ports[0]);
fp << " : 1'bz;" << std::endl;
/* Print timing info */
@ -311,7 +311,7 @@ void print_verilog_and_or_gate_body(std::fstream& fp,
for (const auto& output_port : output_ports) {
for (const auto& output_pin : circuit_lib.pins(output_port)) {
BasicPort output_port_info(circuit_lib.port_prefix(output_port), output_pin, output_pin);
BasicPort output_port_info(circuit_lib.port_lib_name(output_port), output_pin, output_pin);
fp << "\tassign " << generate_verilog_port(VERILOG_PORT_CONKT, output_port_info);
fp << " = ";
@ -323,7 +323,7 @@ void print_verilog_and_or_gate_body(std::fstream& fp,
fp << " " << gate_verilog_operator << " ";
}
BasicPort input_port_info(circuit_lib.port_prefix(input_port), input_pin, input_pin);
BasicPort input_port_info(circuit_lib.port_lib_name(input_port), input_pin, input_pin);
fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info);
/* Increment the counter for port */
@ -395,10 +395,10 @@ void print_verilog_mux2_gate_body(std::fstream& fp,
* the third input is the select port
*/
fp << "\tassign ";
BasicPort out_port_info(circuit_lib.port_prefix(output_ports[0]), 0, 0);
BasicPort sel_port_info(circuit_lib.port_prefix(input_ports[2]), 0, 0);
BasicPort in0_port_info(circuit_lib.port_prefix(input_ports[0]), 0, 0);
BasicPort in1_port_info(circuit_lib.port_prefix(input_ports[1]), 0, 0);
BasicPort out_port_info(circuit_lib.port_lib_name(output_ports[0]), 0, 0);
BasicPort sel_port_info(circuit_lib.port_lib_name(input_ports[2]), 0, 0);
BasicPort in0_port_info(circuit_lib.port_lib_name(input_ports[0]), 0, 0);
BasicPort in1_port_info(circuit_lib.port_lib_name(input_ports[1]), 0, 0);
fp << generate_verilog_port(VERILOG_PORT_CONKT, out_port_info);
fp << " = ";