[FPGA-SPICE] Add VDD and VSS port to module definition
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615a24999a
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@ -18,6 +18,7 @@
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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#include "spice_constants.h"
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#include "spice_writer_utils.h"
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/* begin namespace openfpga */
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@ -98,7 +99,9 @@ std::string generate_spice_port(const BasicPort& port,
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* module <module_name> (<ports without directions>);
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***********************************************/
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void print_spice_subckt_definition(std::fstream& fp,
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const ModuleManager& module_manager, const ModuleId& module_id) {
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const ModuleManager& module_manager,
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const ModuleId& module_id,
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const bool& include_supply_ports) {
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VTR_ASSERT(true == valid_file_stream(fp));
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print_spice_comment(fp, std::string("SPICE module for " + module_manager.module_name(module_id)));
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@ -153,6 +156,29 @@ void print_spice_subckt_definition(std::fstream& fp,
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}
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}
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}
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/* Add supply ports if specified */
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if (true == include_supply_ports) {
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/* Check if we need a new line */
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new_line = false;
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if (10 == pin_cnt) {
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pin_cnt = 0;
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fp << std::endl;
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new_line = true;
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}
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/* Print VDD and VSS ports
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* TODO: the supply ports should be derived from module manager
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*/
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if (true == new_line) {
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std::string port_whitespace(module_head_line.length() - 2, ' ');
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fp << "+ " << port_whitespace;
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}
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write_space_to_file(fp, 1);
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fp << SPICE_SUBCKT_VDD_PORT_NAME;
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write_space_to_file(fp, 1);
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fp << SPICE_SUBCKT_GND_PORT_NAME;
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}
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fp << std::endl;
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}
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@ -43,7 +43,9 @@ std::string generate_spice_port(const BasicPort& port,
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const bool& omit_pin_zero = false);
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void print_spice_subckt_definition(std::fstream& fp,
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const ModuleManager& module_manager, const ModuleId& module_id);
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const ModuleManager& module_manager,
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const ModuleId& module_id,
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const bool& include_supply_ports = true);
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void print_spice_subckt_end(std::fstream& fp,
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const std::string& module_name);
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