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OpenFPGA
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formulate file name, module name and instance name to be consistent

This commit is contained in:
tangxifan 2020-07-24 12:23:27 -06:00
parent fefcd88f14
commit be5966475e
2 changed files with 4 additions and 3 deletions
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5
openfpga/src/base/openfpga_naming.cpp
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@ -238,7 +238,7 @@ std::string generate_routing_block_netlist_name(const std::string& prefix,
std::string generate_routing_block_netlist_name(const std::string& prefix,
const vtr::Point<size_t>& coordinate,
const std::string& postfix) {
return std::string( prefix + std::to_string(coordinate.x()) + std::string("_") + std::to_string(coordinate.y()) + postfix );
return std::string( prefix + std::to_string(coordinate.x()) + std::string("__") + std::to_string(coordinate.y()) + std::string("_") + postfix );
}
/*********************************************************************
@ -1183,8 +1183,9 @@ std::string generate_grid_block_instance_name(const std::string& prefix,
module_name += generate_grid_block_netlist_name(block_name, is_block_io, io_side, std::string());
module_name += std::string("_");
module_name += std::to_string(grid_coord.x());
module_name += std::string("_");
module_name += std::string("__");
module_name += std::to_string(grid_coord.y());
module_name += std::string("_");
return module_name;
}

2
openfpga/src/fpga_verilog/verilog_grid.cpp
View File

@ -270,7 +270,7 @@ void print_verilog_physical_tile_netlist(NetlistManager& netlist_manager,
/* Give a name to the Verilog netlist */
/* Create the file name for Verilog */
std::string verilog_fname(subckt_dir
+ generate_grid_block_netlist_name(std::string(phy_block_type->name),
+ generate_grid_block_netlist_name(std::string(GRID_MODULE_NAME_PREFIX) + std::string(phy_block_type->name),
is_io_type(phy_block_type),
border_side,
std::string(VERILOG_NETLIST_FILE_POSTFIX))