[Tool] Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches

2021-01-22 16:42:13 -07:00 · 2021-01-22 16:42:13 -07:00 · d2defebee9
parent 1823eb857d
commit d2defebee9
1 changed files with 5 additions and 0 deletions
--- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
@ -273,6 +273,11 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
        continue;
      }

+      /* Bypass unused output pads */
+      if (ModuleManager::MODULE_GPOUT_PORT == module_manager.port_type(top_module, module_io_port_id)) {
+        continue;
+      }
+
      /* Wire to a contant */
      BasicPort module_unused_io_port = module_manager.module_port(top_module, module_io_port_id);
      /* Set the port pin index */