[FPGA-SPICE] Add SPICE writer for routing blocks
This commit is contained in:
tangxifan
parent
0f25b52907
commit
5e78e91fdf
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@ -41,6 +41,7 @@ int write_fabric_spice(OpenfpgaContext& openfpga_ctx,
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openfpga_ctx.mutable_spice_netlists(),
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openfpga_ctx.arch(),
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openfpga_ctx.mux_lib(),
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openfpga_ctx.device_rr_gsb(),
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options);
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return status;
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@ -16,6 +16,7 @@
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#include "spice_constants.h"
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#include "spice_submodule.h"
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#include "spice_routing.h"
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/* Header file for this source file */
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#include "spice_api.h"
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@ -41,6 +42,7 @@ int fpga_fabric_spice(const ModuleManager& module_manager,
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NetlistManager& netlist_manager,
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const Arch& openfpga_arch,
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const MuxLibrary& mux_lib,
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const DeviceRRGSB &device_rr_gsb,
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const FabricSpiceOption& options) {
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vtr::ScopedStartFinishTimer timer("Write SPICE netlists for FPGA fabric\n");
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@ -81,6 +83,20 @@ int fpga_fabric_spice(const ModuleManager& module_manager,
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return status;
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}
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/* Generate routing blocks */
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if (true == options.compress_routing()) {
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print_spice_unique_routing_modules(netlist_manager,
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module_manager,
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device_rr_gsb,
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rr_dir_path);
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} else {
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VTR_ASSERT(false == options.compress_routing());
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print_spice_flatten_routing_modules(netlist_manager,
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module_manager,
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device_rr_gsb,
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rr_dir_path);
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}
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/* Given a brief stats on how many Spice modules have been written to files */
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VTR_LOGV(options.verbose_output(),
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"Written %lu SPICE modules in total\n",
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@ -11,6 +11,7 @@
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#include "module_manager.h"
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#include "openfpga_arch.h"
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#include "mux_library.h"
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#include "device_rr_gsb.h"
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#include "fabric_spice_options.h"
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/********************************************************************
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@ -24,6 +25,7 @@ int fpga_fabric_spice(const ModuleManager& module_manager,
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NetlistManager& netlist_manager,
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const Arch& openfpga_arch,
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const MuxLibrary& mux_lib,
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const DeviceRRGSB &device_rr_gsb,
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const FabricSpiceOption& options);
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} /* end namespace openfpga */
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@ -19,4 +19,8 @@ constexpr char* SPICE_SUBCKT_GND_PORT_NAME = "VSS";
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constexpr char* SPICE_MUX_BASIS_POSTFIX = "_basis";
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constexpr char* SPICE_MEM_POSTFIX = "_mem";
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constexpr char* SB_SPICE_FILE_NAME_PREFIX = "sb_";
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constexpr char* LOGICAL_MODULE_SPICE_FILE_NAME_PREFIX = "logical_tile_";
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constexpr char* GRID_SPICE_FILE_NAME_PREFIX = "grid_";
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#endif
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@ -0,0 +1,346 @@
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/*********************************************************************
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* This file includes functions that are used for
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* SPICE generation of FPGA routing architecture (global routing)
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*********************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_time.h"
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#include "vtr_log.h"
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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/* Include FPGA-Verilog header files*/
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#include "openfpga_naming.h"
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#include "spice_constants.h"
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#include "spice_writer_utils.h"
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#include "spice_subckt_writer.h"
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#include "spice_routing.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Print the sub-circuit of a connection Box (Type: [CHANX|CHANY])
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* Actually it is very similiar to switch box but
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* the difference is connection boxes connect Grid INPUT Pins to channels
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* NOTE: direct connection between CLBs should NOT be included inside this
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* module! They should be added in the top-level module as their connection
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* is not limited to adjacent CLBs!!!
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*
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* Location of a X- and Y-direction Connection Block in FPGA fabric
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* +------------+ +-------------+
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* | |------>| |
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* | CLB |<------| Y-direction |
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* | | ... | Connection |
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* | |------>| Block |
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* +------------+ +-------------+
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* | ^ ... | | ^ ... |
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* v | v v | v
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* +-------------------+ +-------------+
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* --->| |--->| |
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* <---| X-direction |<---| Switch |
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* ...| Connection block |... | Block |
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* --->| |--->| |
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* +-------------------+ +-------------+
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*
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* Internal structure:
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* This is an example of a X-direction connection block
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* Note that middle output ports are shorted wire from inputs of routing tracks,
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* which are also the inputs of routing multiplexer of the connection block
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*
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* CLB Input Pins
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* (IPINs)
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* ^ ^ ^
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* | | ... |
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* +--------------------------+
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* | ^ ^ ^ |
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* | | | ... | |
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* | +--------------------+ |
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* | | routing | |
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* | | multiplexers | |
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* | +--------------------+ |
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* | middle outputs |
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* | of routing channel |
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* | ^ ^ ^ ^ ^ ^ ^ ^ |
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* | | | | | ... | | | | |
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* in[0] -->|------------------------->|---> out[0]
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* out[1] <--|<-------------------------|<--- in[1]
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* | ... |
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* in[W-2] -->|------------------------->|---> out[W-2]
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* out[W-1] <--|<-------------------------|<--- in[W-1]
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* +--------------------------+
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*
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* W: routing channel width
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*
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********************************************************************/
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static
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void print_spice_routing_connection_box_unique_module(NetlistManager& netlist_manager,
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const ModuleManager& module_manager,
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const std::string& subckt_dir,
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const RRGSB& rr_gsb,
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const t_rr_type& cb_type) {
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/* Create the netlist */
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vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
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std::string spice_fname(subckt_dir + generate_connection_block_netlist_name(cb_type, gsb_coordinate, std::string(SPICE_NETLIST_FILE_POSTFIX)));
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/* Create the file stream */
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std::fstream fp;
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fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
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check_file_stream(spice_fname.c_str(), fp);
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print_spice_file_header(fp, std::string("SPICE modules for Unique Connection Blocks[" + std::to_string(rr_gsb.get_cb_x(cb_type)) + "]["+ std::to_string(rr_gsb.get_cb_y(cb_type)) + "]"));
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/* Create a Verilog Module based on the circuit model, and add to module manager */
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ModuleId cb_module = module_manager.find_module(generate_connection_block_module_name(cb_type, gsb_coordinate));
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VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
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/* Write the spice module */
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write_spice_subckt_to_file(fp, module_manager, cb_module);
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/* Add an empty line as a splitter */
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fp << std::endl;
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/* Close file handler */
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fp.close();
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/* Add fname to the netlist name list */
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NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
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VTR_ASSERT(NetlistId::INVALID() != nlist_id);
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netlist_manager.set_netlist_type(nlist_id, NetlistManager::ROUTING_MODULE_NETLIST);
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}
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/*********************************************************************
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* Generate the SPICE module for a Switch Box.
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* A Switch Box module consists of following ports:
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* 1. Channel Y [x][y] inputs
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* 2. Channel X [x+1][y] inputs
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* 3. Channel Y [x][y-1] outputs
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* 4. Channel X [x][y] outputs
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* 5. Grid[x][y+1] Right side outputs pins
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* 6. Grid[x+1][y+1] Left side output pins
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* 7. Grid[x+1][y+1] Bottom side output pins
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* 8. Grid[x+1][y] Top side output pins
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* 9. Grid[x+1][y] Left side output pins
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* 10. Grid[x][y] Right side output pins
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* 11. Grid[x][y] Top side output pins
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* 12. Grid[x][y+1] Bottom side output pins
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*
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* Location of a Switch Box in FPGA fabric:
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*
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* -------------- --------------
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* | | | |
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* | Grid | ChanY | Grid |
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* | [x][y+1] | [x][y+1] | [x+1][y+1] |
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* | | | |
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* -------------- --------------
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* ----------
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* ChanX | Switch | ChanX
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* [x][y] | Box | [x+1][y]
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* | [x][y] |
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* ----------
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* -------------- --------------
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* | | | |
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* | Grid | ChanY | Grid |
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* | [x][y] | [x][y] | [x+1][y] |
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* | | | |
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* -------------- --------------
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*
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* Switch Block pin location map
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*
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* Grid[x][y+1] ChanY[x][y+1] Grid[x+1][y+1]
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* right_pins inputs/outputs left_pins
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* | ^ |
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* | | |
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* v v v
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* +-----------------------------------------------+
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* | |
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* Grid[x][y+1] | | Grid[x+1][y+1]
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* bottom_pins---->| |<---- bottom_pins
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* | |
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* ChanX[x][y] | Switch Box [x][y] | ChanX[x+1][y]
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* inputs/outputs<--->| |<---> inputs/outputs
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* | |
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* Grid[x][y+1] | | Grid[x+1][y+1]
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* top_pins---->| |<---- top_pins
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* | |
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* +-----------------------------------------------+
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* ^ ^ ^
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* | | |
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* | v |
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* Grid[x][y] ChanY[x][y] Grid[x+1][y]
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* right_pins inputs/outputs left_pins
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*
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*
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********************************************************************/
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static
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void print_spice_routing_switch_box_unique_module(NetlistManager& netlist_manager,
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const ModuleManager& module_manager,
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const std::string& subckt_dir,
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const RRGSB& rr_gsb) {
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/* Create the netlist */
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vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
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std::string spice_fname(subckt_dir + generate_routing_block_netlist_name(SB_SPICE_FILE_NAME_PREFIX, gsb_coordinate, std::string(SPICE_NETLIST_FILE_POSTFIX)));
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/* Create the file stream */
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std::fstream fp;
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fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
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check_file_stream(spice_fname.c_str(), fp);
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print_spice_file_header(fp, std::string("SPICE subcircuits for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]"));
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/* Create a Verilog Module based on the circuit model, and add to module manager */
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ModuleId sb_module = module_manager.find_module(generate_switch_block_module_name(gsb_coordinate));
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VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
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/* Write the spice module */
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write_spice_subckt_to_file(fp, module_manager, sb_module);
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/* Close file handler */
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fp.close();
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/* Add fname to the netlist name list */
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NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
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VTR_ASSERT(NetlistId::INVALID() != nlist_id);
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netlist_manager.set_netlist_type(nlist_id, NetlistManager::ROUTING_MODULE_NETLIST);
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}
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/********************************************************************
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* Iterate over all the connection blocks in a device
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* and build a module for each of them
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*******************************************************************/
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static
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void print_spice_flatten_connection_block_modules(NetlistManager& netlist_manager,
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const ModuleManager& module_manager,
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const DeviceRRGSB& device_rr_gsb,
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const std::string& subckt_dir,
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const t_rr_type& cb_type) {
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/* Build unique X-direction connection block modules */
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vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
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for (size_t ix = 0; ix < cb_range.x(); ++ix) {
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for (size_t iy = 0; iy < cb_range.y(); ++iy) {
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/* Check if the connection block exists in the device!
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* Some of them do NOT exist due to heterogeneous blocks (height > 1)
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* We will skip those modules
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*/
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const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
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if (true != rr_gsb.is_cb_exist(cb_type)) {
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continue;
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}
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print_spice_routing_connection_box_unique_module(netlist_manager,
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module_manager,
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subckt_dir,
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rr_gsb, cb_type);
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}
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}
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}
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/********************************************************************
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* A top-level function of this file
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* Print all the modules for global routing architecture of a FPGA fabric
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* in Verilog format in a flatten way:
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* Each connection block and switch block will be generated as a unique module
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* Covering:
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* 1. Connection blocks
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* 2. Switch blocks
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*******************************************************************/
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void print_spice_flatten_routing_modules(NetlistManager& netlist_manager,
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const ModuleManager& module_manager,
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const DeviceRRGSB& device_rr_gsb,
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const std::string& subckt_dir) {
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/* Create a vector to contain all the Verilog netlist names that have been generated in this function */
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std::vector<std::string> netlist_names;
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vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
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/* Build unique switch block modules */
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for (size_t ix = 0; ix < sb_range.x(); ++ix) {
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for (size_t iy = 0; iy < sb_range.y(); ++iy) {
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const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
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if (true != rr_gsb.is_sb_exist()) {
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continue;
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}
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print_spice_routing_switch_box_unique_module(netlist_manager,
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module_manager,
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subckt_dir,
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rr_gsb);
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}
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}
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print_spice_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, subckt_dir, CHANX);
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print_spice_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, subckt_dir, CHANY);
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/*
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VTR_LOG("Writing header file for routing submodules '%s'...",
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ROUTING_VERILOG_FILE_NAME);
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print_spice_netlist_include_header_file(netlist_names,
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subckt_dir.c_str(),
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ROUTING_VERILOG_FILE_NAME);
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VTR_LOG("Done\n");
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VTR_LOG("\n");
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*/
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}
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/********************************************************************
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* A top-level function of this file
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* Print all the unique modules for global routing architecture of a FPGA fabric
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* in Verilog format, including:
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* 1. Connection blocks
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* 2. Switch blocks
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*
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* Note: this function SHOULD be called only when
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* the option compact_routing_hierarchy is turned on!!!
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*******************************************************************/
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void print_spice_unique_routing_modules(NetlistManager& netlist_manager,
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const ModuleManager& module_manager,
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const DeviceRRGSB& device_rr_gsb,
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const std::string& subckt_dir) {
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/* Create a vector to contain all the Verilog netlist names that have been generated in this function */
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std::vector<std::string> netlist_names;
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/* Build unique switch block modules */
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for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
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const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
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print_spice_routing_switch_box_unique_module(netlist_manager,
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module_manager,
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subckt_dir,
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unique_mirror);
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}
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/* Build unique X-direction connection block modules */
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for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) {
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const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb);
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print_spice_routing_connection_box_unique_module(netlist_manager,
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module_manager,
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subckt_dir,
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unique_mirror, CHANX);
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}
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/* Build unique X-direction connection block modules */
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for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) {
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const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb);
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print_spice_routing_connection_box_unique_module(netlist_manager,
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module_manager,
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subckt_dir,
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unique_mirror, CHANY);
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}
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/*
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VTR_LOG("Writing header file for routing submodules '%s'...",
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ROUTING_VERILOG_FILE_NAME);
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print_spice_netlist_include_header_file(netlist_names,
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subckt_dir.c_str(),
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ROUTING_VERILOG_FILE_NAME);
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VTR_LOG("Done\n");
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*/
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VTR_LOG("\n");
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}
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} /* end namespace openfpga */
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@ -0,0 +1,32 @@
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#ifndef SPICE_ROUTING_H
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#define SPICE_ROUTING_H
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||||
/********************************************************************
|
||||
* Include header files that are required by function declaration
|
||||
*******************************************************************/
|
||||
|
||||
#include "mux_library.h"
|
||||
#include "module_manager.h"
|
||||
#include "netlist_manager.h"
|
||||
#include "device_rr_gsb.h"
|
||||
|
||||
/********************************************************************
|
||||
* Function declaration
|
||||
*******************************************************************/
|
||||
|
||||
/* begin namespace openfpga */
|
||||
namespace openfpga {
|
||||
|
||||
void print_spice_flatten_routing_modules(NetlistManager& netlist_manager,
|
||||
const ModuleManager& module_manager,
|
||||
const DeviceRRGSB& device_rr_gsb,
|
||||
const std::string& subckt_dir);
|
||||
|
||||
void print_spice_unique_routing_modules(NetlistManager& netlist_manager,
|
||||
const ModuleManager& module_manager,
|
||||
const DeviceRRGSB& device_rr_gsb,
|
||||
const std::string& subckt_dir);
|
||||
|
||||
} /* end namespace openfpga */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue