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[Engine] Fix a few bugs in the BL/WL arrangement and now bitstream generator is working fine

This commit is contained in:
tangxifan 2021-09-10 15:05:46 -07:00
parent 35c7b09888
commit ba1e277dc9
6 changed files with 42 additions and 29 deletions
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9
openfpga/src/fabric/build_top_module_memory.cpp
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@ -75,7 +75,12 @@ void organize_top_module_tile_cb_modules(ModuleManager& module_manager,
if (0 < find_module_num_config_bits(module_manager, cb_module,
circuit_lib, sram_model,
sram_orgz_type)) {
vtr::Point<int> config_coord(rr_gsb.get_cb_x(cb_type) * 2, rr_gsb.get_cb_y(cb_type) * 2);
/* CBX coordinate conversion calculation: (1,0) -> (2,1) */
vtr::Point<int> config_coord(rr_gsb.get_cb_x(cb_type) * 2, rr_gsb.get_cb_y(cb_type) * 2 + 1);
if (cb_type == CHANY) {
/* CBY has a different coordinate conversion calculation: (0,1) -> (1,2) */
config_coord.set(rr_gsb.get_cb_x(cb_type) * 2 + 1, rr_gsb.get_cb_y(cb_type) * 2);
}
/* Note that use the original CB coodinate for instance id searching ! */
module_manager.add_configurable_child(top_module, cb_module, cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)], config_coord);
}
@ -692,7 +697,7 @@ TopModuleNumConfigBits find_top_module_regional_num_config_bit(const ModuleManag
ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id];
vtr::Point<int> coord = module_manager.region_configurable_child_coordinates(top_module, config_region)[child_id];
num_bls[coord.x()] = std::max(num_bls[coord.x()], find_memory_decoder_data_size(find_module_num_config_bits(module_manager, child_module, circuit_lib, sram_model, config_protocol_type)));
num_wls[coord.y()] = std::max(num_wls[coord.y()], find_memory_decoder_data_size(find_module_num_config_bits(module_manager, child_module, circuit_lib, sram_model, config_protocol_type)));
num_wls[coord.y()] = std::max(num_wls[coord.y()], find_memory_wl_decoder_data_size(find_module_num_config_bits(module_manager, child_module, circuit_lib, sram_model, config_protocol_type)));
}
for (const auto& kv : num_bls) {
num_config_bits[config_region].first += kv.second;

19
openfpga/src/fabric/build_top_module_memory_bank.cpp
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@ -323,7 +323,7 @@ void add_top_module_nets_cmos_ql_memory_bank_config_bus(ModuleManager& module_ma
for (size_t child_id = 0; child_id < module_manager.region_configurable_children(top_module, config_region).size(); ++child_id) {
ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id];
vtr::Point<int> coord = module_manager.region_configurable_child_coordinates(top_module, config_region)[child_id];
int child_num_unique_blwls = find_memory_decoder_data_size(find_module_num_config_bits(module_manager, child_module, circuit_lib, sram_model, CONFIG_MEM_QL_MEMORY_BANK));
int child_num_unique_blwls = num_bls_per_tile.at(coord.x());
size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[child_id];
@ -334,12 +334,11 @@ void add_top_module_nets_cmos_ql_memory_bank_config_bus(ModuleManager& module_ma
size_t cur_bl_index = 0;
for (const size_t& sink_bl_pin : child_bl_port_info.pins()) {
size_t bl_pin_id = bl_start_index_per_tile[coord.x()] + cur_bl_index % child_num_unique_blwls;
/* Find the BL decoder data index:
* It should be the starting index plus an offset which is the residual when divided by the number of BLs in this tile
*/
size_t bl_pin_id = bl_start_index_per_tile[coord.x()] + std::floor(cur_bl_index / child_num_unique_blwls);
if (!(bl_pin_id < bl_decoder_dout_port_info.pins().size()))
VTR_ASSERT(bl_pin_id < bl_decoder_dout_port_info.pins().size());
VTR_ASSERT(bl_pin_id < bl_decoder_dout_port_info.pins().size());
/* Create net */
ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
@ -352,7 +351,6 @@ void add_top_module_nets_cmos_ql_memory_bank_config_bus(ModuleManager& module_ma
module_manager.add_module_net_sink(top_module, net,
child_module, child_instance, child_bl_port, sink_bl_pin);
/* Increment the BL index */
cur_bl_index++;
}
}
@ -366,7 +364,7 @@ void add_top_module_nets_cmos_ql_memory_bank_config_bus(ModuleManager& module_ma
for (size_t child_id = 0; child_id < module_manager.region_configurable_children(top_module, config_region).size(); ++child_id) {
ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id];
vtr::Point<int> coord = module_manager.region_configurable_child_coordinates(top_module, config_region)[child_id];
int child_num_unique_blwls = find_memory_decoder_data_size(find_module_num_config_bits(module_manager, child_module, circuit_lib, sram_model, CONFIG_MEM_QL_MEMORY_BANK));
int child_num_unique_blwls = num_bls_per_tile.at(coord.x());
size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[child_id];
@ -377,10 +375,8 @@ void add_top_module_nets_cmos_ql_memory_bank_config_bus(ModuleManager& module_ma
size_t cur_wl_index = 0;
for (const size_t& sink_wl_pin : child_wl_port_info.pins()) {
/* Find the WL decoder data index:
* It should be the starting index plus an offset which is the residual when divided by the number of WLs in this tile
*/
size_t wl_pin_id = wl_start_index_per_tile[coord.x()] + cur_wl_index % child_num_unique_blwls;
size_t wl_pin_id = wl_start_index_per_tile[coord.y()] + std::floor(cur_wl_index / child_num_unique_blwls);
VTR_ASSERT(wl_pin_id < wl_decoder_dout_port_info.pins().size());
/* Create net */
ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
@ -392,8 +388,7 @@ void add_top_module_nets_cmos_ql_memory_bank_config_bus(ModuleManager& module_ma
/* Add net sink */
module_manager.add_module_net_sink(top_module, net,
child_module, child_instance, child_wl_port, sink_wl_pin);
/* Increment the WL index */
cur_wl_index++;
}
}

21
openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.cpp
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@ -54,7 +54,7 @@ void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(const B
const std::map<int, size_t>& num_wls_per_tile,
const std::map<int, size_t>& wl_start_index_per_tile,
vtr::Point<int>& tile_coord,
size_t& cur_mem_index,
std::map<vtr::Point<int>, size_t>& cur_mem_index,
FabricBitstream& fabric_bitstream,
const FabricBitRegionId& fabric_bitstream_region) {
@ -83,9 +83,7 @@ void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(const B
ModuleId child_module = configurable_children[child_id];
size_t child_instance = module_manager.region_configurable_child_instances(parent_module, config_region)[child_id];
if (parent_module == top_module) {
tile_coord = module_manager.region_configurable_child_coordinates(parent_module, config_region)[child_id];
}
tile_coord = module_manager.region_configurable_child_coordinates(parent_module, config_region)[child_id];
/* Get the instance name and ensure it is not empty */
std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance);
@ -95,11 +93,6 @@ void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(const B
/* We must have one valid block id! */
VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block));
/* Reset the memory index for each children under the top-level module */
if (parent_module == top_module) {
cur_mem_index = 0;
}
/* Go recursively */
rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(bitstream_manager, child_block,
module_manager, top_module, child_module,
@ -168,11 +161,11 @@ void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(const B
FabricBitId fabric_bit = fabric_bitstream.add_bit(config_bit);
/* Find BL address */
size_t cur_bl_index = bl_start_index_per_tile.at(tile_coord.x()) + std::floor(cur_mem_index / num_bls_per_tile.at(tile_coord.x()));
size_t cur_bl_index = bl_start_index_per_tile.at(tile_coord.x()) + cur_mem_index[tile_coord] % num_bls_per_tile.at(tile_coord.x());
std::vector<char> bl_addr_bits_vec = itobin_charvec(cur_bl_index, bl_addr_size);
/* Find WL address */
size_t cur_wl_index = wl_start_index_per_tile.at(tile_coord.y()) + cur_mem_index % num_wls_per_tile.at(tile_coord.y());
size_t cur_wl_index = wl_start_index_per_tile.at(tile_coord.y()) + std::floor(cur_mem_index[tile_coord] / num_bls_per_tile.at(tile_coord.x()));
std::vector<char> wl_addr_bits_vec = itobin_charvec(cur_wl_index, wl_addr_size);
/* Set BL address */
@ -188,7 +181,7 @@ void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(const B
fabric_bitstream.add_bit_to_region(fabric_bitstream_region, fabric_bit);
/* Increase the memory index */
cur_mem_index++;
cur_mem_index[tile_coord]++;
}
}
@ -223,8 +216,6 @@ void build_module_fabric_dependent_bitstream_ql_memory_bank(const ConfigProtocol
/* Build bitstreams by region */
for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
size_t cur_mem_index = 0;
/* Find port information for local BL and WL decoder in this region */
std::vector<ModuleId> configurable_children = module_manager.region_configurable_children(top_module, config_region);
VTR_ASSERT(2 <= configurable_children.size());
@ -258,6 +249,8 @@ void build_module_fabric_dependent_bitstream_ql_memory_bank(const ConfigProtocol
std::map<int, size_t> wl_start_index_per_tile = compute_memory_bank_regional_blwl_start_index_per_tile(child_y_range, num_wls_per_tile);
vtr::Point<int> temp_coord;
std::map<vtr::Point<int>, size_t> cur_mem_index;
rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(bitstream_manager, top_block,
module_manager, top_module, top_module,
config_region,

18
openfpga/src/utils/decoder_library_utils.cpp
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@ -86,6 +86,24 @@ size_t find_memory_decoder_data_size(const size_t& num_mems) {
return (size_t)std::ceil(std::sqrt((float)num_mems));
}
/***************************************************************************************
* Find the size of WL data lines for a memory decoder to access a memory array
* This function is applicable to a memory bank organization where BL data lines
* is the dominant factor. It means that the BL data lines is strictly an integeter close
* to the square root of the number of memory cells.
* For example, 203 memory cells leads to 15 BLs to control
* The WL data lines may not be exactly the same as the number of BLs.
* Considering the example of 203 memory cells again, when 15 BLs are used, we just need
* 203 / 15 = 13.5555 -> 14 WLs
***************************************************************************************/
size_t find_memory_wl_decoder_data_size(const size_t& num_mems) {
/* Handle exception: zero memory should have zero WLs */
if (0 == num_mems) {
return 0;
}
return std::ceil(num_mems / (size_t)std::ceil(std::sqrt((float)num_mems)));
}
/***************************************************************************************
* Try to find if the decoder already exists in the library,
* If there is no such decoder, add it to the library

2
openfpga/src/utils/decoder_library_utils.h
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@ -17,6 +17,8 @@ size_t find_memory_decoder_addr_size(const size_t& num_mems);
size_t find_memory_decoder_data_size(const size_t& num_mems);
size_t find_memory_wl_decoder_data_size(const size_t& num_mems);
DecoderId add_mux_local_decoder_to_library(DecoderLibrary& decoder_lib,
const size_t data_size);

2
openfpga/src/utils/memory_bank_utils.cpp
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@ -82,7 +82,7 @@ std::map<int, size_t> compute_memory_bank_regional_wordline_numbers_per_tile(con
for (size_t child_id = 0; child_id < module_manager.region_configurable_children(top_module, config_region).size(); ++child_id) {
ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id];
vtr::Point<int> coord = module_manager.region_configurable_child_coordinates(top_module, config_region)[child_id];
num_wls_per_tile[coord.y()] = std::max(num_wls_per_tile[coord.y()], find_memory_decoder_data_size(find_module_num_config_bits(module_manager, child_module, circuit_lib, sram_model, CONFIG_MEM_QL_MEMORY_BANK)));
num_wls_per_tile[coord.y()] = std::max(num_wls_per_tile[coord.y()], find_memory_wl_decoder_data_size(find_module_num_config_bits(module_manager, child_module, circuit_lib, sram_model, CONFIG_MEM_QL_MEMORY_BANK)));
}
return num_wls_per_tile;