[Tool] Add '--fabric_netlist' option to 'write_preconfigured_testbench' command
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@ -221,6 +221,7 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
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CommandOptionId opt_output_dir = cmd.option("file");
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CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
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CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path");
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CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
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CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
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CommandOptionId opt_verbose = cmd.option("verbose");
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@ -230,6 +231,7 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
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*/
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VerilogTestbenchOption options;
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options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
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options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
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options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
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options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
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options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
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@ -239,6 +239,10 @@ ShellCommandId add_openfpga_write_preconfigured_testbench_command(openfpga::Shel
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* add an option '--fabric_netlist_file_path'*/
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CommandOptionId fabric_netlist_opt = shell_cmd.add_option("fabric_netlist_file_path", false, "specify the file path to the fabric hdl netlist");
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shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING);
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/* Add an option '--pin_constraints_file in short '-pcf' */
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CommandOptionId pcf_opt = shell_cmd.add_option("pin_constraints_file", false, "Specify the file path to the pin constraints");
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shell_cmd.set_option_short_name(pcf_opt, "pcf");
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